Stefano Gallucci
Orcid: 0009-0002-0049-5595
According to our database1,
Stefano Gallucci authored at least 8 papers
between 1993 and 2026.
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Bibliography
2026
A -66dBc-Worst-Fractional-Spur and 58fs-Jitter Fractional-N Digital PLL Using a Supply-Resilient Pseudo-Differential Inverse-Constant-Slope DTC.
Proceedings of the IEEE International Solid-State Circuits Conference, 2026
A Fractional-N Digital PLL with a Supply-Insensitive DTC Achieving -62dBc Spur and 69fs Jitter Under 10mVpp Sinusoidal DTC Supply Ripple and 6.2mVrms DTC Supply Noise.
Proceedings of the IEEE International Solid-State Circuits Conference, 2026
A DTC-Based Digital PLL Achieving -64.5dBc Fractional Spur and 80fs Jitter with a 2-Track Probability-Density-Shaping ΔΣ Modulator and a Dithered-Threshold TDC.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2026
A 4.75GHz Digital PLL Achieving 30.4fs jitter under 5mVpp Supply Ripples Using a Voltage-Biased Oscillator with Adaptive Supply Sensitivity Cancellation and Common-Mode Resonance Tuning.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2026
2025
A Low-Noise Digital PLL With an Adaptive Common-Mode Resonance Tuning Technique for Voltage-Biased Oscillators.
IEEE J. Solid State Circuits, December, 2025
34.3 A 4.75GHz Digital PLL with 45.8fs Integrated-Jitter and 257dB FoM Based on a Voltage-Biased Harmonic-Shaping DCO with Adaptive Common-Mode Resonance Tuning.
Proceedings of the IEEE International Solid-State Circuits Conference, 2025
34.2 A 380μW and -242.8dB FoM Digital-PLL-Based GFSK Modulator with Sub-20μs Settling Frequency Hopping for Bluetooth Low-Energy in 22nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2025
1993
Proceedings of the Fifth International Conference on Tools with Artificial Intelligence, 1993