Andrea L. Lacaita

Proceedings of the IEEE International Solid-State Circuits Conference, 2024

10.1 An 8.75GHz Fractional-N Digital PLL with a Reverse-Concavity Variable-Slope DTC Achieving 57.3fsrms Integrated Jitter and -252.4dB FoM.

[BibT_eX]

[DOI]

Michele Rossoni

Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2023

A Low-Spur and Low-Jitter Fractional-N Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, December, 2023

A Novel LO Phase-Shifting System Based on Digital Bang-Bang PLLs With Background Phase-Offset Correction for Integrated Phased Arrays.

[BibT_eX]

[DOI]

Francesco Tesolin

IEEE J. Solid State Circuits, September, 2023

A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner.

[BibT_eX]

[DOI]

Francesco Buccoleri

IEEE J. Solid State Circuits, March, 2023

Phase Noise Analysis of Periodically ON/OFF Switched Oscillators.

[BibT_eX]

[DOI]

Giacomo Castoro

IEEE Trans. Circuits Syst. I Regul. Pap., January, 2023

A 2GS/s 11b 8x Interleaved ADC with 9.2 ENOB and 69.9dB SFDR in 28nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

A 76.7fs-lntegrated-Jitter and -71.9dBc In-Band Fractional-Spur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid- State Circuits Conference, 2023

A 9.25GHz Digital PLL with Fractional-Spur Cancellation Based on a Multi-DTC Topology.

[BibT_eX]

[DOI]

Giacomo Castoro

Proceedings of the IEEE International Solid- State Circuits Conference, 2023

2022

A 900-MS/s SAR-Based Time-Interleaved ADC With a Fully Programmable Interleaving Factor and On-Chip Scalable Background Calibrations.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2022

Novel Feed-Forward Technique for Digital Bang-Bang PLL to Achieve Fast Lock and Low Phase Noise.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

A 12.5-GHz Fractional-N Type-I Sampling PLL Achieving 58-fs Integrated Jitter.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2022

Analysis and Design of 8-to-101.6-GHz Injection-Locked Frequency Divider by Five With Concurrent Dual-Path Multi-Injection Topology.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2022

A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping.

[BibT_eX]

[DOI]

Michael Peter Kennedy

IEEE J. Solid State Circuits, 2022

A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking-Time.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2022

A 68.6fs<sub>rms</sub>-Total-integrated-Jitter and 1.5µs-LocKing-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2022

A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler.

[BibT_eX]

[DOI]

Francesco Buccoleri

Proceedings of the IEEE Custom Integrated Circuits Conference, 2022

2021

A Generalization of the Groszkowski's Result in Differential Oscillator Topologies.

[BibT_eX]

[DOI]

Francesco Buccoleri

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

32.8 A 98.4fs-Jitter 12.9-to-15.1GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays.

[BibT_eX]

[DOI]

Alessio Santiccioli

Mario Mercandelli

Michael Peter Kennedy

Proceedings of the IEEE International Solid-State Circuits Conference, 2021

A 12.9-to-15.1GHz Digital PLL Based on a Bang-Bang Phase Detector with Adaptively Optimized Noise Shaping Achieving 107.6fs Integrated Jitter.

[BibT_eX]

[DOI]

Mario Mercandelli

Alessio Santiccioli

Michael Peter Kennedy

Proceedings of the IEEE International Solid-State Circuits Conference, 2021

A PLL-Based Digital Technique for Orthogonal Correction of ADC Non-Linearity.

[BibT_eX]

[DOI]

Proceedings of the 28th IEEE International Conference on Electronics, 2021

A 13.6-69.1GHz 5.6mW Ring-Type Injection-Locked Frequency Divider by Five with >20% Continuous Locking Range and Operation up to 101.6GHz in 28nm CMOS.

[BibT_eX]

[DOI]

David Seebacher

Matteo Bassi

Proceedings of the IEEE Custom Integrated Circuits Conference, 2021

2020

A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-N Bang-Bang PLL With Digital Frequency-Error Recovery for Fast Locking.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2020

17.2 A 66fsrmsJitter 12.8-to-15.2GHz Fractional-N Bang-Bang PLL with Digital Frequency-Error Recovery for Fast Locking.

[BibT_eX]

[DOI]

Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

17.5 A 12.5GHz Fractional-N Type-I Sampling PLL Achieving 58fs Integrated Jitter.

[BibT_eX]

[DOI]

Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2019

Time-Variant Modeling and Analysis of Multiplying Delay-Locked Loops.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

A Novel Single-Inductor Injection-Locked Frequency Divider by Three With Dual-Injection Secondary Locking.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

A 1.6-to-3.0-GHz Fractional-N MDLL With a Digital-to-Time Converter Range-Reduction Technique Achieving 397-fs Jitter at 2.5-mW Power.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2019

A 30-GHz Digital Sub-Sampling Fractional- $N$ PLL With -238.6-dB Jitter-Power Figure of Merit in 65-nm LP CMOS.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2019

A 30GHz Digital Sub-Sampling Fractional-N PLL with 198fsrms Jitter in 65nm LP CMOS.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid- State Circuits Conference, 2019

Current Transport in Polysilicon-channel GAA MOSFETs: A Modeling Perspective.

[BibT_eX]

[DOI]

Aurelio Mannara

Proceedings of the 49th European Solid-State Device Research Conference, 2019

A 1.6-to-3.0-GHz Fractional-N MDLL with a Digital-to-Time Converter Range-Reduction Technique Achieving 397fs Jitter at 2.5-mW Power.

[BibT_eX]

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

2018

High Scale-Factor Stability Frequency-Modulated MEMS Gyroscope: 3-Axis Sensor and Integrated Electronics Design.

[BibT_eX]

[DOI]

Giacomo Langfelder

IEEE Trans. Ind. Electron., 2018

Efficient Behavioral Simulation of Charge-Pump Phase-Locked Loops.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2018

A Background Calibration Technique to Control the Bandwidth of Digital PLLs.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2018

Impact of CMOS Scaling on Switched-Capacitor Power Amplifiers.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

A Low-Power and Wide-Locking-Range Injection-Locked Frequency Divider by Three with Dual-Injection Divide-by-Two Technique.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

A Single-Inductor Two-Step-Mixing Injection-Locked Frequency Divider by Four with Concurrent Tail-Injection.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

Random Dopant Fluctuation and Random Telegraph Noise in Nanowire and Macaroni MOSFETs.

[BibT_eX]

[DOI]

Proceedings of the 48th European Solid-State Device Research Conference, 2018

2017

Reviewing the Evolution of the NAND Flash Technology.

[BibT_eX]

[DOI]

Akira Goda

Peter Feeley

Angelo Visconti

Proc. IEEE, 2017

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices.

[BibT_eX]

[DOI]

Comput., 2017

A novel segmentation scheme for DTC-based ΔΣ fractional-N PLL.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016

A 64-Channel 965-µW Neural Recording SoC With UWB Wireless Transmission in 130-nm CMOS.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2016

An efficient tool for the assisted design of SAR ADCs capacitive DACs.

[BibT_eX]

[DOI]

Integr., 2016

Bipolar-switching operated phase change memory (PCM) for improved high-temperature reliability.

[BibT_eX]

[DOI]

Proceedings of the 46th European Solid-State Device Research Conference, 2016

2015

A 1.7 GHz Fractional-N Frequency Synthesizer Based on a Multiplying Delay-Locked Loop.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2015

Fundamental Power Limits of SAR and ΔΣ Analog-to-Digital Converters.

[BibT_eX]

[DOI]

Proceedings of the Nordic Circuits and Systems Conference, 2015

A tool for the assisted design of charge redistribution SAR ADCs.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014

A Modeling Environment for the Simulation and Design of Charge Redistribution DACs Used in SAR ADCs.

[BibT_eX]

[DOI]

Proceedings of the UKSim-AMSS 16th International Conference on Computer Modelling and Simulation, 2014

A simulation and modeling environment for the analysis and design of charge redistribution DACs used in SAR ADCs.

[BibT_eX]

[DOI]

Proceedings of the 37th International Convention on Information and Communication Technology, 2014

Analysis and optimization of a SAR ADC with attenuation capacitor.

[BibT_eX]

[DOI]

Proceedings of the 37th International Convention on Information and Communication Technology, 2014

2.9 A Background calibration technique to control bandwidth in digital PLLs.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

21.1 A 1.7GHz MDLL-based fractional-N frequency synthesizer with 1.4ps RMS integrated jitter and 3mW power using a 1b TDC.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

Cycling-induced threshold-voltage instabilities in nanoscale NAND flash memories: Sensitivity to the array background pattern.

[BibT_eX]

[DOI]

Angelo Visconti

Proceedings of the 44th European Solid State Device Research Conference, 2014

Data regeneration and disturb immunity of T-RAM cells.

[BibT_eX]

[DOI]

A. Benvenuti

Proceedings of the 44th European Solid State Device Research Conference, 2014

2013

Suppression of Flicker Noise Up-Conversion in a 65-nm CMOS VCO in the 3.0-to-3.6 GHz Band.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2013

A Wideband Fractional-N PLL With Suppressed Charge-Pump Noise and Automatic Loop Filter Calibration.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2013

Simulating phase noise induced from cyclostationary noise sources.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

A spur cancellation technique for MDLL-based frequency synthesizers.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Background adaptive linearization of high-speed digital-to-analog Converters.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Accelerated reliability testing of flash memory: Accuracy and issues on a 45nm NOR technology.

[BibT_eX]

[DOI]

Marcello Calabrese

Carmine Miccoli

Angelo Visconti

Proceedings of 2013 International Conference on IC Design & Technology, 2013

2012

Efficient Calculation of the Impulse Sensitivity Function in Oscillators.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2012

Flicker Noise Up-Conversion due to Harmonic Distortion in Van der Pol CMOS Oscillators.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2012

A 20 Mb/s Phase Modulator Based on a 3.6 GHz Digital PLL With -36 dB EVM at 5 mW Power.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2012

A fast and accurate simulation method of impulse sensitivity function in oscillators.

[BibT_eX]

[DOI]

Federico Pepe

Proceedings of the 2012 Proceedings of the 35th International Convention, 2012

A 20Mb/s phase modulator based on a 3.6GHz digital PLL with -36dB EVM at 5mW power.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2011

Low-Power Divider Retiming in a 3-4 GHz Fractional-N PLL.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2011

A Wideband 3.6 GHz Digital ΔΣ Fractional-N PLL With Phase Interpolation Divider and Digital Spur Cancellation.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2011

A 2.9-4.0-GHz Fractional-N Digital PLL With Bang-Bang Phase Detector and 560-fs<sub>rms</sub> Integrated Jitter at 4.5-mW Power.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2011

A 2.9-to-4.0GHz fractional-N digital PLL with bang-bang phase detector and 560fsrms integrated jitter at 4.5mW power.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2011

Multipath adaptive cancellation of divider non-linearity in fractional-N PLLs.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Behavioral phase-noise analysis of charge-pump phase-locked loops.

[BibT_eX]

[DOI]

Proceedings of the 20th European Conference on Circuit Theory and Design, 2011

2010

Time-to-Digital Converter for Frequency Synthesis Based on a Digital Bang-Bang DLL.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2010

Folding of Phase Noise Spectra in Charge-Pump Phase-Locked Loops Induced by Frequency Division.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2010

AD-PLL for WiMAX with Digitally-Regulated TDC and Glitch Correction Logic.

[BibT_eX]

[DOI]

EURASIP J. Embed. Syst., 2010

A 3MHz-BW 3.6GHz digital fractional-N PLL with sub-gate-delay TDC, phase-interpolation divider, and digital mismatch cancellation.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

Suppression of flicker noise upconversion in a 65nm CMOS VCO in the 3.0-to-3.6GHz band.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

Time-to-digital converter with 3-ps resolution and digital linearization algorithm.

[BibT_eX]

[DOI]

Proceedings of the 36th European Solid-State Circuits Conference, 2010

A multi-channel low-power IC for neural spike recording with data compression and narrowband 400-MHz MC-FSK wireless transmission.

[BibT_eX]

[DOI]

Proceedings of the 36th European Solid-State Circuits Conference, 2010

2009

Noise Analysis and Minimization in Bang-Bang Digital PLLs.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2009

A glitch-corrector circuit for low-spur ADPLLs.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International Conference on Electronics, 2009

An all-digital architecture for low-jitter regulated delay lines.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International Conference on Electronics, 2009

2008

Low-Power Signal Component Separator for a 64-QAM 802.11 LINC Transmitter.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2008

2007

Quantization Effects in All-Digital Phase-Locked Loops.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2007

An integrated low-noise multichannel system for neural signals amplification.

[BibT_eX]

[DOI]

Gytis Baranauskas

Proceedings of the 33rd European Solid-State Circuits Conference, 2007

A multistandard Σ-Δ fractional-N frequency synthesizer for 802.11a/b/g WLAN.

[BibT_eX]

[DOI]

Proceedings of the 33rd European Solid-State Circuits Conference, 2007

2006

Matching requirements in LINC transmitters for OFDM signals.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2006

Multiphase LC oscillators.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2006

A varactor configuration minimizing the amplitude-to-phase noise conversion in VCOs.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2006

5-GHz Oscillator Array With Reduced Flicker Up-Conversion in 0.13-$muhboxm$CMOS.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2006

Low-power CMOS IEEE 802.11a/g Signal Separator for Outphasing Transmitter.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

2004

Fast-switching analog PLL with finite-impulse response.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2004

A 13.5-mW 5-GHz frequency synthesizer with dynamic-logic frequency divider.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2004

Phase noise in digital frequency dividers.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2004

Phase noise and accuracy in quadrature oscillators.

[BibT_eX]

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Fast-switching analog PLL with finite-impulse response.

[BibT_eX]

[DOI]

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A multi-tank LC-oscillator [microwave oscillator example].

[BibT_eX]

[DOI]

Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004

Differential tuning oscillators with reduced flicker noise upconversion.

[BibT_eX]

[DOI]

Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004

2003

A DDS-based PLL for 2.4-GHz frequency synthesis.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2003

A voltage-controlled oscillator for IEEE 802.11a and HiperLAN2 application.

[BibT_eX]

[DOI]

Andrea Giovanni Bonfanti

Proceedings of the ESSCIRC 2003, 2003

2002

Frequency dependence on bias current in 5 GHz CMOS VCOs: impact on tuning range and flicker noise upconversion.

[BibT_eX]

[DOI]

Sander L. J. Gierkink

Vito Boccuzzi

IEEE J. Solid State Circuits, 2002

Integrated LC oscillators for frequency synthesis in wireless applications.

[BibT_eX]

[DOI]