Riccardo Moleri

According to our database, Riccardo Moleri authored at least 9 papers between 2024 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2026

A Wideband Digitally Assisted Frequency Tripler With Adaptively Optimized Output Power in 55-nm SiGe BiCMOS.

Daniele Lodi Rizzini, Francesco Tesolin, Michele Rossoni, Riccardo Moleri, Filippo Osio, Andrea Mazzanti, Andrea L. Lacaita, Simone Mattia Dartizio, Salvatore Levantino

IEEE J. Solid State Circuits, May, 2026

A -66dBc-Worst-Fractional-Spur and 58fs-Jitter Fractional-N Digital PLL Using a Supply-Resilient Pseudo-Differential Inverse-Constant-Slope DTC.

Pietro Salvi, Michele Rossoni, Riccardo Moleri, Daniele Lodi Rizzini, Damiano Fagotti, Stefano Gallucci, Andrea Leonardo Lacaita, Simone Mattia Dartizio, Salvatore Levantino

Proceedings of the IEEE International Solid-State Circuits Conference, 2026

A Fractional-N Digital PLL with a Supply-Insensitive DTC Achieving -62dBc Spur and 69fs Jitter Under 10mVpp Sinusoidal DTC Supply Ripple and 6.2mVrms DTC Supply Noise.

Damiano Fagotti, Riccardo Moleri, Michele Rossoni, Daniele Lodi Rizzini, Pietro Salvi, Stefano Gallucci, Giovanni Rocco Trotta, Andrea Leonardo Lacaita, Simone Mattia Dartizio, Salvatore Levantino

Proceedings of the IEEE International Solid-State Circuits Conference, 2026

A DTC-Based Digital PLL Achieving -64.5dBc Fractional Spur and 80fs Jitter with a 2-Track Probability-Density-Shaping ΔΣ Modulator and a Dithered-Threshold TDC.

Riccardo Moleri, Daniele Lodi Rizzini, Michele Rossoni, Damiano Fagotti, Pietro Salvi, Stefano Gallucci, Andrea Leonardo Lacaita, Salvatore Levantino, Simone Mattia Dartizio

Proceedings of the IEEE Custom Integrated Circuits Conference, 2026

A 4.75GHz Digital PLL Achieving 30.4fs jitter under 5mVpp Supply Ripples Using a Voltage-Biased Oscillator with Adaptive Supply Sensitivity Cancellation and Common-Mode Resonance Tuning.

Stefano Gallucci, Daniele Lodi Rizzini, Riccardo Moleri, Michele Rossoni, Pietro Salvi, Damiano Fagotti, Francesco Tesolin, Andrea Leonardo Lacaita, Simone Mattia Dartizio, Salvatore Levantino

Proceedings of the IEEE Custom Integrated Circuits Conference, 2026

2025

A Low-Noise Digital PLL With an Adaptive Common-Mode Resonance Tuning Technique for Voltage-Biased Oscillators.

Stefano Gallucci, Francesco Tesolin, Pietro Salvi, Daniele Lodi Rizzini, Riccardo Moleri, Francesco Buccoleri, Michele Rossoni, Giacomo Castoro, Carlo Samori, Andrea Leonardo Lacaita, Simone Mattia Dartizio, Salvatore Levantino

IEEE J. Solid State Circuits, December, 2025

34.3 A 4.75GHz Digital PLL with 45.8fs Integrated-Jitter and 257dB FoM Based on a Voltage-Biased Harmonic-Shaping DCO with Adaptive Common-Mode Resonance Tuning.

Stefano Gallucci, Francesco Tesolin, Pietro Salvi, Daniele Lodi Rizzini, Riccardo Moleri, Francesco Buccoleri, Michele Rossoni, Giacomo Castoro, Simone Mattia Dartizio, Carlo Samori, Andrea Leonardo Lacaita, Salvatore Levantino

Proceedings of the IEEE International Solid-State Circuits Conference, 2025

34.2 A 380μW and -242.8dB FoM Digital-PLL-Based GFSK Modulator with Sub-20μs Settling Frequency Hopping for Bluetooth Low-Energy in 22nm CMOS.

Simone Mattia Dartizio, Giacomo Castoro, Stefano Gallucci, Michele Rossoni, Riccardo Moleri, Francesco Tesolin, Pietro Salvi, Saleh Karman, Andrea Leonardo Lacaita, Salvatore Levantino

Proceedings of the IEEE International Solid-State Circuits Conference, 2025

2024

A 79.3fsrms Jitter Fractional-N Digital PLL Based on a DTC Chopping Technique.

Riccardo Moleri, Simone Mattia Dartizio, Michele Rossoni, Giacomo Castoro, Francesco Tesolin, Dmytro Cherniak, Carlo Samori, Andrea Leonardo Lacaita, Salvatore Levantino

Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024