Dan Nicolaescu

According to our database1, Dan Nicolaescu authored at least 11 papers between 2000 and 2011.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2011
The world's fastest DSP core: Breaking the 100 GMAC/s barrier.
Proceedings of the 2011 IEEE Hot Chips 23 Symposium (HCS), 2011

2006
Fast Speculative Address Generation and Way Caching for Reducing L1 Data Cache Energy.
Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

2005
Using a Way Cache to Improve Performance of Set-Associative Caches.
Proceedings of the High-Performance Computing - 6th International Symposium, 2005

2004
Caching Values in the Load Store Queue.
Proceedings of the 12th International Workshop on Modeling, 2004

Low Energy, Highly-Associative Cache Design for Embedded Processors.
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

Energy-Efficient Design for Highly Associative Instruction Caches in Next-Generation Embedded Processors.
Proceedings of the 2004 Design, 2004

2003
Reducing data cache energy consumption via cached load/store queue.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

Reducing Power Consumption for High-Associativity Data Caches in Embedded Processors.
Proceedings of the 2003 Design, 2003

Low Energy Associative Data Caches for Embedded Systems.
Proceedings of the Embedded Software for SoC, 2003

2000
Compiler-Directed Cache Assist Adaptivity.
Proceedings of the High Performance Computing, Third International Symposium, 2000

Compiler-Directed Cache Line Size Adaptivity.
Proceedings of the Intelligent Memory Systems, Second International Workshop, 2000


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