Alexander V. Veidenbaum
Affiliations:- University of California, Irvine, USA
According to our database1,
Alexander V. Veidenbaum
authored at least 145 papers
between 1986 and 2023.
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on ics.uci.edu
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Bibliography
2023
Torchhd: An Open Source Python Library to Support Research on Hyperdimensional Computing and Vector Symbolic Architectures.
J. Mach. Learn. Res., 2023
IACR Cryptol. ePrint Arch., 2023
DotHash: Estimating Set Similarity Metrics for Link Prediction and Document Deduplication.
Proceedings of the 29th ACM SIGKDD Conference on Knowledge Discovery and Data Mining, 2023
Using Hyperdimensional Computing to Extract Features for the Detection of Type 2 Diabetes.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2023
2022
Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
2021
Proceedings of the 43rd Annual International Conference of the IEEE Engineering in Medicine & Biology Society, 2021
Proceedings of the 43rd Annual International Conference of the IEEE Engineering in Medicine & Biology Society, 2021
2020
Proceedings of the 2020 IEEE International Parallel and Distributed Processing Symposium Workshops, 2020
2019
Proceedings of the IEEE International Parallel and Distributed Processing Symposium Workshops, 2019
Proceedings of the 2019 IEEE International Parallel and Distributed Processing Symposium, 2019
AFFIX: Automatic Acceleration Framework for FPGA Implementation of OpenVX Vision Algorithms.
Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019
2018
An empirical study of the effect of source-level loop transformations on compiler stability.
Proc. ACM Program. Lang., 2018
Proceedings of the 9th ACM Multimedia Systems Conference, 2018
Proceedings of the Languages and Compilers for Parallel Computing, 2018
Proceedings of the Languages and Compilers for Parallel Computing, 2018
Proceedings of the 26th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2018
2017
J. Parallel Distributed Comput., 2017
IACR Cryptol. ePrint Arch., 2017
Proceedings of the Languages and Compilers for Parallel Computing, 2017
Proceedings of the 2017 IEEE International Symposium on Workload Characterization, 2017
2016
J. Parallel Distributed Comput., 2016
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2016
Proceedings of the Languages and Compilers for Parallel Computing, 2016
Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016
2015
Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015
Proceedings of the 13th IEEE Symposium on Embedded Systems For Real-time Multimedia, 2015
2014
Proceedings of the XIVth International Conference on Embedded Computer Systems: Architectures, 2014
Proceedings of the XIVth International Conference on Embedded Computer Systems: Architectures, 2014
A Compilation and Run-Time Framework for Maximizing Performance of Self-scheduling Algorithms.
Proceedings of the Network and Parallel Computing, 2014
Author retrospective for compiler-directed data prefetching in multiprocessors with memory hierarchies.
Proceedings of the ACM International Conference on Supercomputing 25th Anniversary Volume, 2014
Proceedings of the Computing Frontiers Conference, CF'14, 2014
2013
Proceedings of the International Symposium on Quality Electronic Design, 2013
Proceedings of the IEEE 12th International Symposium on Parallel and Distributed Computing, 2013
Proceedings of the Compiler Construction - 22nd International Conference, 2013
Proceedings of the Advanced Parallel Processing Technologies, 2013
2012
Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012
Proceedings of the Languages and Compilers for Parallel Computing, 2012
Proceedings of the 19th International Conference on High Performance Computing, 2012
Proceedings of the Computing Frontiers Conference, CF'12, 2012
Proceedings of the 15th International Conference on Compilers, 2012
2011
MZZ-HVS: Multiple Sleep Modes Zig-Zag Horizontal and Vertical Sleep Transistor Sharing to Reduce Leakage Power in On-Chip SRAM Peripheral Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2011
Reducing Power in All Major CAM and SRAM-Based Processor Units via Centralized, Dynamic Resource Size Management.
IEEE Trans. Very Large Scale Integr. Syst., 2011
On leakage power optimization in clock tree networks for ASICs and general-purpose processors.
Sustain. Comput. Informatics Syst., 2011
Pruning hardware evaluation space via correlation-driven application similarity analysis.
Proceedings of the 8th Conference on Computing Frontiers, 2011
2010
Proceedings of the first joint WOSP/SIPEW International Conference on Performance Engineering, 2010
Post-synthesis sleep transistor insertion for leakage power optimization in clock tree networks.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010
Exploiting power budgeting in thermal-aware dynamic placement for reconfigurable systems.
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010
RELOCATE: Register File Local Access Pattern Redistribution Mechanism for Power and Thermal Management in Out-of-Order Embedded Processor.
Proceedings of the High Performance Embedded Architectures and Compilers, 2010
Proceedings of the 7th Conference on Computing Frontiers, 2010
Multiple sleep modes leakage control in peripheral circuits of a all major SRAM-based processor units.
Proceedings of the 7th Conference on Computing Frontiers, 2010
2009
ACM Trans. Embed. Comput. Syst., 2009
A configurable simulation environment for the efficient simulation of large-scale spiking neural networks on graphics processors.
Neural Networks, 2009
Int. J. Parallel Program., 2009
Proceedings of of SYSTOR 2009: The Israeli Experimental Systems Conference 2009, 2009
Proceedings of the Computer Performance Evaluation and Benchmarking, 2009
Proceedings of the 23rd IEEE International Symposium on Parallel and Distributed Processing, 2009
Efficient simulation of large-scale Spiking Neural Networks using CUDA graphics processors.
Proceedings of the International Joint Conference on Neural Networks, 2009
Proceedings of the 23rd international conference on Supercomputing, 2009
Proceedings of the ICPP 2009, 2009
2008
ACM Trans. Embed. Comput. Syst., 2008
J. Syst. Archit., 2008
A hardware mechanism to reduce the energy consumption of the register file of in-order architectures.
Int. J. Embed. Syst., 2008
Comparative architectural characterization of SPEC CPU2000 and CPU2006 benchmarks on the intel® Core<sup>TM</sup> 2 Duo processor.
Proceedings of the 2008 International Conference on Embedded Computer Systems: Architectures, 2008
Proceedings of the 2008 International Conference on Embedded Computer Systems: Architectures, 2008
Proceedings of the 13th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2008
Proceedings of the 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41 2008), 2008
Improving performance and reducing energy-delay with adaptive resource resizing for out-of-order embedded processors.
Proceedings of the 2008 ACM SIGPLAN/SIGBED Conference on Languages, 2008
Impact of JVM superoperators on energy consumption in resource-constrained embedded systems.
Proceedings of the 2008 ACM SIGPLAN/SIGBED Conference on Languages, 2008
Proceedings of the 35th International Symposium on Computer Architecture (ISCA 2008), 2008
Proceedings of the 26th International Conference on Computer Design, 2008
ZZ-HVS: Zig-zag horizontal and vertical sleep transistor sharing to reduce leakage power in on-chip SRAM peripheral circuits.
Proceedings of the 26th International Conference on Computer Design, 2008
Dynamic register file resizing and frequency scaling to improve embedded processor performance and energy-delay efficiency.
Proceedings of the 45th Design Automation Conference, 2008
Multiple sleep mode leakage control for cache peripheral circuits in embedded processors.
Proceedings of the 2008 International Conference on Compilers, 2008
2007
A predictive decode filter cache for reducing power consumption in embedded processors.
ACM Trans. Design Autom. Electr. Syst., 2007
Proceedings of the 2007 ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Systems, 2007
Tight analysis of the performance potential of thread speculation using spec CPU 2006.
Proceedings of the 12th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2007
Novel Brain-Derived Algorithms Scale Linearly with Number of Processing Elements.
Proceedings of the Parallel Computing: Architectures, 2007
Proceedings of the 25th International Conference on Computer Design, 2007
A simplified java bytecode compilation system for resource-constrained embedded processors.
Proceedings of the 2007 International Conference on Compilers, 2007
2006
On the performance potential of different types of speculative thread-level parallelism: The DL version of this paper includes corrections that were not made available in the printed proceedings.
Proceedings of the 20th Annual International Conference on Supercomputing, 2006
Fast Speculative Address Generation and Way Caching for Reducing L1 Data Cache Energy.
Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006
Proceedings of the Euro-Par 2006, Parallel Processing, 12th International Euro-Par Conference, Dresden, Germany, August 28, 2006
Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006
2005
Line Size Adaptivity Analysis of Parameterized Loop Nests for Direct Mapped Data Cache.
IEEE Trans. Computers, 2005
Proceedings of the High-Performance Computing - 6th International Symposium, 2005
Proceedings of the High-Performance Computing - 6th International Symposium, 2005
Proceedings of the 19th Annual International Conference on Supercomputing, 2005
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005
Proceedings of the EMSOFT 2005, 2005
Proceedings of the Advances in Computer Systems Architecture, 10th Asia-Pacific Conference, 2005
2004
Int. J. High Perform. Comput. Netw., 2004
Proceedings of the Power-Aware Computer Systems, 4th International Workshop, 2004
Proceedings of the 12th International Workshop on Modeling, 2004
Proceedings of the 31st International Symposium on Computer Architecture (ISCA 2004), 2004
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004
Energy-Efficient Design for Highly Associative Instruction Caches in Next-Generation Embedded Processors.
Proceedings of the 2004 Design, 2004
2003
Int. J. Parallel Program., 2003
Guest Editors' Introduction: Application-Specific Microprocessors.
IEEE Des. Test Comput., 2003
Proceedings of the Languages and Compilers for Parallel Computing, 2003
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003
Proceedings of the High Performance Computing, 5th International Symposium, 2003
Improving Branch Prediction Accuracy in Embedded Processors in the Presence of Context Switches.
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003
Reducing Power Consumption for High-Associativity Data Caches in Embedded Processors.
Proceedings of the 2003 Design, 2003
Proceedings of the 14th IEEE International Conference on Application-Specific Systems, 2003
Proceedings of the Embedded Software for SoC, 2003
2002
Integrated I-cache Way Predictor and Branch Target Buffer to Reduce Energy Consumption.
Proceedings of the High Performance Computing, 4th International Symposium, 2002
Proceedings of the 2002 Design, 2002
2001
2000
On Interaction between Interconnection Network Design and Latency Hiding Techniques in Multiprocessors.
J. Supercomput., 2000
Proceedings of the High Performance Computing, Third International Symposium, 2000
Proceedings of the Intelligent Memory Systems, Second International Workshop, 2000
1999
Interconnection network organization and its impact on performance and cost in shared memory multiprocessors.
Parallel Comput., 1999
An Integrated Hardware/Software Data Prefetching Scheme for Shared-Memory Multiprocessors.
Int. J. Parallel Program., 1999
Int. J. High Speed Comput., 1999
Proceedings of the 13th international conference on Supercomputing, 1999
1998
Proceedings of the 25 Years of the International Symposia on Computer Architecture (Selected Papers)., 1998
1997
Proceedings of the High Performance Computing, International Symposium, 1997
Proceedings of the 1997 International Conference on Parallel Processing (ICPP '97), 1997
The Effect of Limited Network Bandwidth and its Utilization by Latency Hiding Techniques in Large-Scale Shared Memory Systems.
Proceedings of the 1997 Conference on Parallel Architectures and Compilation Techniques (PACT '97), 1997
1995
Int. J. Parallel Program., 1995
Proceedings of the 7th Annual ACM Symposium on Parallel Algorithms and Architectures, 1995
1994
Proceedings of the Proceedings Supercomputing '94, 1994
1993
Proceedings of the 20th Annual International Symposium on Computer Architecture, 1993
Proceedings of the 1993 International Conference on Parallel Processing, 1993
1992
Proceedings of the Proceedings Supercomputing '92, 1992
1991
Proceedings of the Proceedings Supercomputing '91, 1991
Proceedings of the Proceedings Supercomputing '91, 1991
Proceedings of the Fifth International Parallel Processing Symposium, Proceedings, Anaheim, California, USA, April 30, 1991
Proceedings of the 5th international conference on Supercomputing, 1991
The Organization of the Cedar System.
Proceedings of the International Conference on Parallel Processing, 1991
An Integrated Hardware/Software Solution for Effective Management of Local Storage in High-Performance Systems.
Proceedings of the International Conference on Parallel Processing, 1991
Preliminary Performance Analysis of the Cedar Multiprocessor Memory System.
Proceedings of the International Conference on Parallel Processing, 1991
1990
Proceedings of the 4th international conference on Supercomputing, 1990
1989
Proceedings of the 3rd international conference on Supercomputing, 1989
1988
Proceedings of the 15th Annual International Symposium on Computer Architecture, 1988
Proceedings of the 2nd international conference on Supercomputing, 1988
Stale Data Detection and Coherence Enforcement Using Flow Analysis.
Proceedings of the International Conference on Parallel Processing, 1988
1987
The Performance of Software-managed Multiprocessor Caches on Parallel Numerical Programs.
Proceedings of the Supercomputing, 1987
1986
A Compiler-Assisted Cache Coherence Solution for Multiprcessors.
Proceedings of the International Conference on Parallel Processing, 1986