Danilo Vendraminetto

Orcid: 0000-0002-5321-6513

According to our database1, Danilo Vendraminetto authored at least 12 papers between 2013 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

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Bibliography

2020
Reducing Interpolant Circuit Size Through SAT-Based Weakening.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

2019
Logic Synthesis for Interpolant Circuit Compaction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Model Checking Speculation-Dependent Security Properties: Abstracting and Reducing Processor Models for Sound and Complete Verification.
Proceedings of the Codes, Cryptology and Information Security, 2019

2017
Embedded Systems Secure Path Verification at the Hardware/Software Interface.
IEEE Des. Test, 2017

Interpolation-Based Learning as a Mean to Speed-Up Bounded Model Checking (Short Paper).
Proceedings of the Software Engineering and Formal Methods - 15th International Conference, 2017

2016
Advanced Techniques for Bit-Level Model Checking.
PhD thesis, 2016

Secure Path Verification.
Proceedings of the 1st IEEE International Verification and Security Workshop, 2016

Reducing interpolant circuit size by ad-hoc logic synthesis and SAT-based weakening.
Proceedings of the 2016 Formal Methods in Computer-Aided Design, 2016

2014
Hardware Model Checking Competition 2014: An Analysis and Comparison of Solvers and Benchmarks.
J. Satisf. Boolean Model. Comput., 2014

Tightening BDD-based approximate reachability with SAT-based clause generalization<sup>∗</sup>.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
Fast cone-of-influence computation and estimation in problems with multiple properties.
Proceedings of the Design, Automation and Test in Europe, 2013

Optimization techniques for craig interpolant compaction in unbounded model checking.
Proceedings of the Design, Automation and Test in Europe, 2013


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