Paolo Camurati
Orcid: 0000-0002-2476-2160
According to our database1,
Paolo Camurati
authored at least 79 papers
between 1986 and 2022.
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Bibliography
2022
Interpolation with guided refinement: revisiting incrementality in SAT-based unbounded model checking.
Formal Methods Syst. Des., April, 2022
2021
Optimizing Binary Decision Diagrams for Interpretable Machine Learning Classification.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
2019
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
KPIs for Optimal Location of charging stations for Electric Vehicles: the Biella case-study.
Proceedings of the 2019 Federated Conference on Computer Science and Information Systems, 2019
Model Checking Speculation-Dependent Security Properties: Abstracting and Reducing Processor Models for Sound and Complete Verification.
Proceedings of the Codes, Cryptology and Information Security, 2019
2018
To split or to group: from divide-and-conquer to sub-task sharing for verifying multiple properties in model checking.
Int. J. Softw. Tools Technol. Transf., 2018
2017
Formal Methods Syst. Des., 2017
IEEE Des. Test, 2017
Interpolation-Based Learning as a Mean to Speed-Up Bounded Model Checking (Short Paper).
Proceedings of the Software Engineering and Formal Methods - 15th International Conference, 2017
2016
A graph-labeling approach for efficient cone-of-influence computation in model-checking problems with multiple properties.
Softw. Pract. Exp., 2016
Proceedings of the 1st IEEE International Verification and Security Workshop, 2016
Proceedings of the 2016 Formal Methods in Computer-Aided Design, 2016
A 7/2-Approximation Algorithm for the Maximum Duo-Preservation String Mapping Problem.
Proceedings of the 27th Annual Symposium on Combinatorial Pattern Matching, 2016
2009
Speeding up model checking by exploiting explicit and hidden verification constraints.
Proceedings of the Design, Automation and Test in Europe, 2009
2008
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008
Trading-Off SAT Search and Variable Quantifications for Effective Unbounded Model Checking.
Proceedings of the Formal Methods in Computer-Aided Design, 2008
2002
Proceedings of the 2002 Design, 2002
Proceedings of the 39th Design Automation Conference, 2002
2001
Reachability analysis of large circuits using disjunctive partitioning and partial iterative squaring.
J. Syst. Archit., 2001
Proceedings of the Conference on Design, Automation and Test in Europe, 2001
2000
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000
J. Syst. Archit., 2000
Verification of Similar FSMs by Mixing Incremental Re-encoding, Reachability Analysis, and Combinational Checks.
Formal Methods Syst. Des., 2000
1999
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999
Proceedings of the 1999 Design, 1999
Proceedings of the 36th Conference on Design Automation, 1999
1998
Auxiliary variables for BDD-based representation and manipulation of Boolean functions.
ACM Trans. Design Autom. Electr. Syst., 1998
Softw. Pract. Exp., 1998
Formal Methods Syst. Des., 1998
1997
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997
Proceedings of the European Design and Test Conference, 1997
Disjunctive Partitioning and Partial Iterative Squaring: An Effective Approach for Symbolic Traversal of Large Circuits.
Proceedings of the 34st Conference on Design Automation, 1997
A parallel approach to symbolic traversal based on set partitioning.
Proceedings of the Advances in Hardware Design and Verification, 1997
1996
Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996
Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996
Proceedings of the conference on European design automation, 1996
Proceedings of the conference on European design automation, 1996
1995
Proceedings of the Proceedings EURO-DAC'95, 1995
Proceedings of the Correct Hardware Design and Verification Methods, 1995
1994
Proceedings of the 12th IEEE VLSI Test Symposium (VTS'94), 1994
Proceedings of the 12th IEEE VLSI Test Symposium (VTS'94), 1994
Proceedings of the Proceedings IEEE International Test Conference 1994, 1994
Detecting hard faults with combined approximate forward/backward symbolic techniques.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994
Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994
Proceedings of the Fourth Great Lakes Symposium on Design Automation of High Performance VLSI Systems, 1994
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994
Proceedings of the Proceedings EURO-DAC'94, 1994
Proceedings of the 31st Conference on Design Automation, 1994
1993
J. Electron. Test., 1993
Exploiting Cofactoring for Efficient FSM Symbolic Traversal Based on the Transition Relation.
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993
An efficient tool for system-level verification of behaviors and temporal properties.
Proceedings of the European Design Automation Conference 1993, 1993
Exploiting Symbolic Traversal Techniques for Efficient Process Algebra Manipulation.
Proceedings of the Computer Hardware Description Languages and their Applications, Proceedings of the 11th IFIP WG10.2 International Conference on Computer Hardware Description Languages and their Applications, 1993
Proceedings of the Correct Hardware Design and Verification Methods, 1993
Proceedings of the Correct Hardware Design and Verification Methods, 1993
1992
A simulation-based approach to test pattern generation for synchronous sequential circuits.
Proceedings of the 10th IEEE VLSI Test Symposium (VTS'92), 1992
Proceedings of the Proceedings IEEE International Test Conference 1992, 1992
Proceedings of the conference on European design automation, 1992
Proceedings of the 29th Design Automation Conference, 1992
1991
Proceedings of the First Great Lakes Symposium on VLSI, 1991
Proceedings of the conference on European design automation, 1991
1990
Microprocessing and Microprogramming, 1990
Microprocessing and Microprogramming, 1990
J. Electron. Test., 1990
Proceedings of the Proceedings IEEE International Test Conference 1990, 1990
Proceedings of the European Design Automation Conference, 1990
Proceedings of the Computer-Aided Verification, 1990
Proceedings of the Computer Aided Verification, 2nd International Workshop, 1990
1989
Microprocess. Microsystems, 1989
Microprocessing and Microprogramming, 1989
Expressing logical and temporal conditions in simulation environments: TPDL<sup>*</sup>.
Microprocessing and Microprogramming, 1989
1988
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988
Formal Verification of Hardware Correctness: Introduction and Survey of Current Research.
Computer, 1988
Proceedings of the Computer Design: VLSI in Computers and Processors, 1988
Proceedings of the Computer Design: VLSI in Computers and Processors, 1988
1986
Experiences in Prolog-Based DFT Rule Checking.
Proceedings of the Fall Joint Computer Conference, November 2-6, 1986, Dallas, Texas, USA, 1986