Stefano Quer

According to our database1, Stefano Quer authored at least 65 papers between 1994 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2018
To split or to group: from divide-and-conquer to sub-task sharing for verifying multiple properties in model checking.
STTT, 2018

A Fast MPEG's CDVS Implementation for GPU Featured in Mobile Devices.
IEEE Access, 2018

2017
Moving Object Detection in Heterogeneous Conditions in Embedded Systems.
Sensors, 2017

Efficient Complex High-Precision Computations on GPUs without Precision Loss.
Journal of Circuits, Systems, and Computers, 2017

2016
A graph-labeling approach for efficient cone-of-influence computation in model-checking problems with multiple properties.
Softw., Pract. Exper., 2016

Street Viewer: An Autonomous Vision Based Traffic Tracking System.
Sensors, 2016

A 7/2-Approximation Algorithm for the Maximum Duo-Preservation String Mapping Problem.
Proceedings of the 27th Annual Symposium on Combinatorial Pattern Matching, 2016

2015
CDVS feature selection on embedded systems.
Proceedings of the 2015 IEEE International Conference on Multimedia & Expo Workshops, 2015

2014
Model checking evaluation of airplane landing trajectories.
STTT, 2014

Hardware Model Checking Competition 2014: An Analysis and Comparison of Solvers and Benchmarks.
JSAT, 2014

Tightening BDD-based approximate reachability with SAT-based clause generalization.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
Thread-based multi-engine model checking for multicore platforms.
ACM Trans. Design Autom. Electr. Syst., 2013

Fast cone-of-influence computation and estimation in problems with multiple properties.
Proceedings of the Design, Automation and Test in Europe, 2013

2011
Benchmarking a model checker for algorithmic improvements and tuning for performance.
Formal Methods in System Design, 2011

Interpolation sequences revisited.
Proceedings of the Design, Automation and Test in Europe, 2011

2010
A Novel SAT-Based Approach to the Task Graph Cost-Optimal Scheduling Problem.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2010

Partitioning Interpolant-Based Verification for Effective Unbounded Model Checking.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2010

2009
Strengthening Model Checking Techniques With Inductive Invariants.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2009

Speeding up model checking by exploiting explicit and hidden verification constraints.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
Boosting interpolation with dynamic localized abstraction and redundancy removal.
ACM Trans. Design Autom. Electr. Syst., 2008

A Probabilistic and Approximated Approach to Circuit-Based Formal Verification.
JSAT, 2008

Stressing Symbolic Scheduling Techniques within Aircraft Maintenance Optimization.
JSAT, 2008

Trading-Off SAT Search and Variable Quantifications for Effective Unbounded Model Checking.
Proceedings of the Formal Methods in Computer-Aided Design, 2008

2007
Boosting the role of inductive invariants in model checking.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006
Stepping forward with interpolants in unbounded model checking.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

2005
Are BDDs still alive within sequential verification?
STTT, 2005

A BMC-based formulation for the scheduling problem of hardware systems.
STTT, 2005

Exploiting Target Enlargement and Dynamic Abstraction within Mixed BDD and SAT Invariant Checking.
Electr. Notes Theor. Comput. Sci., 2005

Circuit Based Quantification: Back to State Set Manipulation within Unbounded Model Checking.
Proceedings of the 2005 Design, 2005

2003
A BMC-formulation for the scheduling problem in highly constrained hardware Systems.
Electr. Notes Theor. Comput. Sci., 2003

Improving SAT-Based Bounded Model Checking by Means of BDD-Based Approximate Traversals.
Proceedings of the 2003 Design, 2003

2002
A Symbolic Approach for the Combined Solution of Scheduling and Allocation.
Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002

Dynamic Scheduling and Clustering in Symbolic Image Computation.
Proceedings of the 2002 Design, 2002

Can BDDs compete with SAT solvers on bounded model checking?
Proceedings of the 39th Design Automation Conference, 2002

Mixing Forward and Backward Traversals in Guided-Prioritized BDD-Based Verification.
Proceedings of the Computer Aided Verification, 14th International Conference, 2002

2001
Reachability analysis of large circuits using disjunctive partitioning and partial iterative squaring.
Journal of Systems Architecture, 2001

Biasing symbolic search by means of dynamic activity profiles.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

2000
Improving symbolic reachability analysis by means of activityprofiles.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2000

Symbolic forward/backward traversals of large finite state machines.
Journal of Systems Architecture, 2000

Verification of Similar FSMs by Mixing Incremental Re-encoding, Reachability Analysis, and Combinational Checks.
Formal Methods in System Design, 2000

Optimizing sequential verification by retiming transformations.
Proceedings of the 37th Conference on Design Automation, 2000

1999
Improving the efficiency of BDD-based operators by means of partitioning.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1999

Computing Timed Transition Relations for Sequential Cycle-Based Simulation.
Proceedings of the 1999 Design, 1999

Improving Symbolic Traversals by Means of Activity Profiles.
Proceedings of the 36th Conference on Design Automation, 1999

Cycle-Based Symbolic Simulation of Gate-Level Synchronous Circuits.
Proceedings of the 36th Conference on Design Automation, 1999

1998
Binary Decision Diagrams and the Multiple Variable Order Problem
Universität Trier, Mathematik/Informatik, Forschungsbericht, 1998

Power optimization of core-based systems by address bus encoding.
IEEE Trans. VLSI Syst., 1998

Auxiliary variables for BDD-based representation and manipulation of Boolean functions.
ACM Trans. Design Autom. Electr. Syst., 1998

Memory Optimization in Function and Set Manipulation with BDDs.
Softw., Pract. Exper., 1998

1997
System-level power optimization of special purpose applications: the beach solution.
Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997

Verification and synthesis of counters based on symbolic techniques.
Proceedings of the European Design and Test Conference, 1997

Disjunctive Partitioning and Partial Iterative Squaring: An Effective Approach for Symbolic Traversal of Large Circuits.
Proceedings of the 34st Conference on Design Automation, 1997

A parallel approach to symbolic traversal based on set partitioning.
Proceedings of the Advances in Hardware Design and Verification, 1997

1996
Enhancing FSM Traversal by Temporary Re-Encoding.
Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996

Improved reachability analysis of large finite state machines.
Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

Decomposed symbolic forward traversals of large finite state machines.
Proceedings of the conference on European design automation, 1996

Incremental re-encoding for symbolic traversal of product machines.
Proceedings of the conference on European design automation, 1996

1995
Computing subsets of equivalence classes for large FSMs.
Proceedings of the Proceedings EURO-DAC'95, 1995

Transforming boolean relations by symbolic encoding.
Proceedings of the Correct Hardware Design and Verification Methods, 1995

1994
Full-Symbolic ATPG for Large Circuits.
Proceedings of the Proceedings IEEE International Test Conference 1994, 1994

Detecting hard faults with combined approximate forward/backward symbolic techniques.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

Efficient State Space Pruning in Symbolic Backward Traversal.
Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

Symbolic traversals of data paths with auxiliary variables.
Proceedings of the Fourth Great Lakes Symposium on Design Automation of High Performance VLSI Systems, 1994

Symbolic exploration of large circuits with enhanced forward/backward traversals.
Proceedings of the Proceedings EURO-DAC'94, 1994

Auxiliary Variables for Extending Symbolic Traversal Techniques to Data Paths.
Proceedings of the 31st Conference on Design Automation, 1994


  Loading...