# Stefano Quer

According to our database

Collaborative distances:

^{1}, Stefano Quer authored at least 71 papers between 1994 and 2020.Collaborative distances:

## Timeline

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#### On csauthors.net:

## Bibliography

2020

Computation, 2020

Proceedings of the 15th International Conference on Software Technologies, 2020

2019

CoRR, 2019

Detecting, Opening and Navigating through Doors: A Unified Framework for Human Service Robots.

Proceedings of the 14th International Conference on Software Technologies, 2019

Service Robots: A Unified Framework for Detecting, Opening and Navigating Through Doors.

Proceedings of the Software Technologies - 14th International Conference, 2019

2018

To split or to group: from divide-and-conquer to sub-task sharing for verifying multiple properties in model checking.

Int. J. Softw. Tools Technol. Transf., 2018

IEEE Access, 2018

2017

Sensors, 2017

Journal of Circuits, Systems, and Computers, 2017

2016

A graph-labeling approach for efficient cone-of-influence computation in model-checking problems with multiple properties.

Softw. Pract. Exp., 2016

Sensors, 2016

CoRR, 2016

A 7/2-Approximation Algorithm for the Maximum Duo-Preservation String Mapping Problem.

Proceedings of the 27th Annual Symposium on Combinatorial Pattern Matching, 2016

2015

Proceedings of the 2015 IEEE International Conference on Multimedia & Expo Workshops, 2015

2014

Int. J. Softw. Tools Technol. Transf., 2014

Hardware Model Checking Competition 2014: An Analysis and Comparison of Solvers and Benchmarks.

J. Satisf. Boolean Model. Comput., 2014

Tightening BDD-based approximate reachability with SAT-based clause generalization<sup>∗</sup>.

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013

ACM Trans. Design Autom. Electr. Syst., 2013

Fast cone-of-influence computation and estimation in problems with multiple properties.

Proceedings of the Design, Automation and Test in Europe, 2013

2011

Benchmarking a model checker for algorithmic improvements and tuning for performance.

Formal Methods Syst. Des., 2011

Proceedings of the Design, Automation and Test in Europe, 2011

2010

IEEE Trans. on CAD of Integrated Circuits and Systems, 2010

Partitioning Interpolant-Based Verification for Effective Unbounded Model Checking.

IEEE Trans. on CAD of Integrated Circuits and Systems, 2010

2009

IEEE Trans. on CAD of Integrated Circuits and Systems, 2009

Speeding up model checking by exploiting explicit and hidden verification constraints.

Proceedings of the Design, Automation and Test in Europe, 2009

2008

ACM Trans. Design Autom. Electr. Syst., 2008

J. Satisf. Boolean Model. Comput., 2008

Stressing Symbolic Scheduling Techniques within Aircraft Maintenance Optimization.

J. Satisf. Boolean Model. Comput., 2008

Trading-Off SAT Search and Variable Quantifications for Effective Unbounded Model Checking.

Proceedings of the Formal Methods in Computer-Aided Design, 2008

2007

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006

Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

2005

Int. J. Softw. Tools Technol. Transf., 2005

Int. J. Softw. Tools Technol. Transf., 2005

Exploiting Target Enlargement and Dynamic Abstraction within Mixed BDD and SAT Invariant Checking.

Electron. Notes Theor. Comput. Sci., 2005

Circuit Based Quantification: Back to State Set Manipulation within Unbounded Model Checking.

Proceedings of the 2005 Design, 2005

2004

Improving SAT-based Bounded Model Checking by Means of BDD-based Approximate Traversals.

J. UCS, 2004

2003

A BMC-formulation for the scheduling problem in highly constrained hardware Systems.

Electron. Notes Theor. Comput. Sci., 2003

2002

Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002

Proceedings of the 2002 Design, 2002

Proceedings of the 39th Design Automation Conference, 2002

Mixing Forward and Backward Traversals in Guided-Prioritized BDD-Based Verification.

Proceedings of the Computer Aided Verification, 14th International Conference, 2002

2001

Reachability analysis of large circuits using disjunctive partitioning and partial iterative squaring.

J. Syst. Archit., 2001

Proceedings of the Conference on Design, Automation and Test in Europe, 2001

2000

IEEE Trans. on CAD of Integrated Circuits and Systems, 2000

J. Syst. Archit., 2000

Verification of Similar FSMs by Mixing Incremental Re-encoding, Reachability Analysis, and Combinational Checks.

Formal Methods Syst. Des., 2000

Proceedings of the 37th Conference on Design Automation, 2000

1999

IEEE Trans. on CAD of Integrated Circuits and Systems, 1999

Proceedings of the 1999 Design, 1999

Proceedings of the 36th Conference on Design Automation, 1999

Proceedings of the 36th Conference on Design Automation, 1999

1998

Binary Decision Diagrams and the Multiple Variable Order Problem

Universität Trier, Mathematik/Informatik, Forschungsbericht, 1998

IEEE Trans. Very Large Scale Integr. Syst., 1998

Auxiliary variables for BDD-based representation and manipulation of Boolean functions.

ACM Trans. Design Autom. Electr. Syst., 1998

Softw. Pract. Exp., 1998

1997

System-level power optimization of special purpose applications: the beach solution.

Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997

Proceedings of the European Design and Test Conference, 1997

Disjunctive Partitioning and Partial Iterative Squaring: An Effective Approach for Symbolic Traversal of Large Circuits.

Proceedings of the 34st Conference on Design Automation, 1997

A parallel approach to symbolic traversal based on set partitioning.

Proceedings of the Advances in Hardware Design and Verification, 1997

1996

Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996

Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

Proceedings of the conference on European design automation, 1996

Proceedings of the conference on European design automation, 1996

1995

Proceedings of the Proceedings EURO-DAC'95, 1995

Proceedings of the Correct Hardware Design and Verification Methods, 1995

1994

Proceedings of the Proceedings IEEE International Test Conference 1994, 1994

Detecting hard faults with combined approximate forward/backward symbolic techniques.

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

Proceedings of the Fourth Great Lakes Symposium on Design Automation of High Performance VLSI Systems, 1994

Proceedings of the Proceedings EURO-DAC'94, 1994

Proceedings of the 31st Conference on Design Automation, 1994