Stefano Quer

Debjit Pal

CoRR, 2024

2023

A Framework for Economic and Environmental Benefit Through Renewable Energy Community.

[BibT_eX]

[DOI]

IEEE Syst. J., December, 2023

Clustering Appliance Operation Modes With Unsupervised Deep Learning Techniques.

[BibT_eX]

[DOI]

IEEE Trans. Ind. Informatics, July, 2023

The Multi-Maximum and Quasi-Maximum Common Subgraph Problem.

[BibT_eX]

[DOI]

Lorenzo Cardone

Comput., 2023

An Experimental Evaluation of Graph Coloring Heuristics on Multi- and Many-Core Architectures.

[BibT_eX]

[DOI]

IEEE Access, 2023

A Toolchain to Quantify Burn-In Stress Effectiveness on Large Automotive System-on-Chips.

[BibT_eX]

[DOI]

IEEE Access, 2023

A Web Scraping Algorithm to Improve the Computation of the Maximum Common Subgraph.

[BibT_eX]

[DOI]

Proceedings of the 18th International Conference on Software Technologies, 2023

2022

A Densely-Deployed, High Sampling Rate, Open-Source Air Pollution Monitoring WSN.

[BibT_eX]

[DOI]

Bartolomeo Montrucchio

Edoardo Giusto

Mohammad Ghazi Vakili

Renato Ferrero

Claudio Fornaro

Dataset, May, 2022

A Smart Meter Infrastructure for Smart Grid IoT Applications.

[BibT_eX]

[DOI]

IEEE Internet Things J., 2022

Parallel Multithread Analysis of Extremely Large Simulation Traces.

[BibT_eX]

[DOI]

IEEE Access, 2022

An innovative Strategy to Quickly Grade Functional Test Programs.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2022

2021

Modules and Techniques for Motion Planning: An Industrial Perspective.

[BibT_eX]

[DOI]

Luz Amanda Garcia

Sensors, 2021

Smart Techniques for Flying-probe Testing.

[BibT_eX]

[DOI]

Andrea Calabrese

Giovanni Squillero

Proceedings of the 16th International Conference on Software Technologies, 2021

Accelerated Analysis of Simulation Dumps through Parallelization on Multicore Architectures.

[BibT_eX]

[DOI]

Proceedings of the 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2021

2020

A Densely-Deployed, High Sampling Rate, Open-Source Air Pollution Monitoring WSN.

[BibT_eX]

[DOI]

Bartolomeo Montrucchio

Edoardo Giusto

Mohammad Ghazi Vakili

Renato Ferrero

Claudio Fornaro

IEEE Trans. Veh. Technol., 2020

The Maximum Common Subgraph Problem: A Parallel and Multi-Engine Approach.

[BibT_eX]

[DOI]

Andrea Marcelli

Giovanni Squillero

Comput., 2020

Graph Reachability on Parallel Many-Core Architectures.

[BibT_eX]

[DOI]

Andrea Calabrese

Comput., 2020

A Parallel Many-core CUDA-based Graph Labeling Computation.

[BibT_eX]

[DOI]

Proceedings of the 15th International Conference on Software Technologies, 2020

2019

The Maximum Common Subgraph Problem: A Portfolio Approach.

[BibT_eX]

[DOI]

Andrea Marcelli

Giovanni Squillero

CoRR, 2019

Detecting, Opening and Navigating through Doors: A Unified Framework for Human Service Robots.

[BibT_eX]

[DOI]

Francesco Savarese

Antonio Tejero-de-Pablos

Tatsuya Harada

Proceedings of the 14th International Conference on Software Technologies, 2019

Service Robots: A Unified Framework for Detecting, Opening and Navigating Through Doors.

[BibT_eX]

[DOI]

Tatsuya Harada

Antonio Tejero-de-Pablos

Francesco Savarese

Proceedings of the Software Technologies - 14th International Conference, 2019

2018

To split or to group: from divide-and-conquer to sub-task sharing for verifying multiple properties in model checking.

[BibT_eX]

[DOI]

Int. J. Softw. Tools Technol. Transf., 2018

A Fast MPEG's CDVS Implementation for GPU Featured in Mobile Devices.

[BibT_eX]

[DOI]

Alessandro Garbo

IEEE Access, 2018

2017

Moving Object Detection in Heterogeneous Conditions in Embedded Systems.

[BibT_eX]

[DOI]

Alessandro Garbo

Sensors, 2017

Efficient Complex High-Precision Computations on GPUs without Precision Loss.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2017

2016

A graph-labeling approach for efficient cone-of-influence computation in model-checking problems with multiple properties.

[BibT_eX]

[DOI]

Softw. Pract. Exp., 2016

Street Viewer: An Autonomous Vision Based Traffic Tracking System.

[BibT_eX]

[DOI]

Sensors, 2016

A Greedy Approach to Answer Reachability Queries on DAGs.

[BibT_eX]

[DOI]

CoRR, 2016

A 7/2-Approximation Algorithm for the Maximum Duo-Preservation String Mapping Problem.

[BibT_eX]

[DOI]

Proceedings of the 27th Annual Symposium on Combinatorial Pattern Matching, 2016

2015

CDVS feature selection on embedded systems.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Conference on Multimedia & Expo Workshops, 2015

2014

Model checking evaluation of airplane landing trajectories.

[BibT_eX]

[DOI]

Int. J. Softw. Tools Technol. Transf., 2014

Hardware Model Checking Competition 2014: An Analysis and Comparison of Solvers and Benchmarks.

[BibT_eX]

[DOI]

J. Satisf. Boolean Model. Comput., 2014

Tightening BDD-based approximate reachability with SAT-based clause generalization<sup>∗</sup>.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013

Thread-based multi-engine model checking for multicore platforms.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2013

Fast cone-of-influence computation and estimation in problems with multiple properties.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

2011

Benchmarking a model checker for algorithmic improvements and tuning for performance.

[BibT_eX]

[DOI]

Formal Methods Syst. Des., 2011

Interpolation sequences revisited.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2011

2010

A Novel SAT-Based Approach to the Task Graph Cost-Optimal Scheduling Problem.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Partitioning Interpolant-Based Verification for Effective Unbounded Model Checking.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

2009

Strengthening Model Checking Techniques With Inductive Invariants.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Speeding up model checking by exploiting explicit and hidden verification constraints.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2009

2008

Boosting interpolation with dynamic localized abstraction and redundancy removal.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2008

A Probabilistic and Approximated Approach to Circuit-Based Formal Verification.

[BibT_eX]

[DOI]

J. Satisf. Boolean Model. Comput., 2008

Stressing Symbolic Scheduling Techniques within Aircraft Maintenance Optimization.

[BibT_eX]

[DOI]

J. Satisf. Boolean Model. Comput., 2008

Trading-Off SAT Search and Variable Quantifications for Effective Unbounded Model Checking.

[BibT_eX]

[DOI]

Proceedings of the Formal Methods in Computer-Aided Design, 2008

2007

Boosting the role of inductive invariants in model checking.

[BibT_eX]

[DOI]

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006

Stepping forward with interpolants in unbounded model checking.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

2005

Are BDDs still alive within sequential verification?

[BibT_eX]

[DOI]

Int. J. Softw. Tools Technol. Transf., 2005

A BMC-based formulation for the scheduling problem of hardware systems.

[BibT_eX]

[DOI]

Int. J. Softw. Tools Technol. Transf., 2005

Circuit Based Quantification: Back to State Set Manipulation within Unbounded Model Checking.

[BibT_eX]

[DOI]

Proceedings of the 2005 Design, 2005

2004

Improving SAT-based Bounded Model Checking by Means of BDD-based Approximate Traversals.

[BibT_eX]

[DOI]

J. Univers. Comput. Sci., 2004

Exploiting Target Enlargement and Dynamic Abstraction within Mixed BDD and SAT Invariant Checking.

[BibT_eX]

[DOI]

Proceedings of the 2nd International Workshop on Bounded Model Checking, 2004

2003

A BMC-formulation for the scheduling problem in highly constrained hardware Systems.

[BibT_eX]

[DOI]

Proceedings of the First International Workshop on Bounded Model Checking, 2003

2002

A Symbolic Approach for the Combined Solution of Scheduling and Allocation.

[BibT_eX]

[DOI]

Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002

Dynamic Scheduling and Clustering in Symbolic Image Computation.

[BibT_eX]

[DOI]

Proceedings of the 2002 Design, 2002

Can BDDs compete with SAT solvers on bounded model checking?

[BibT_eX]

[DOI]

Proceedings of the 39th Design Automation Conference, 2002

Mixing Forward and Backward Traversals in Guided-Prioritized BDD-Based Verification.

[BibT_eX]

[DOI]

Proceedings of the Computer Aided Verification, 14th International Conference, 2002

2001

Reachability analysis of large circuits using disjunctive partitioning and partial iterative squaring.

[BibT_eX]

[DOI]

J. Syst. Archit., 2001

Biasing symbolic search by means of dynamic activity profiles.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2001

2000

Improving symbolic reachability analysis by means of activityprofiles.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Symbolic forward/backward traversals of large finite state machines.

[BibT_eX]

[DOI]

J. Syst. Archit., 2000

Verification of Similar FSMs by Mixing Incremental Re-encoding, Reachability Analysis, and Combinational Checks.

[BibT_eX]

[DOI]

Formal Methods Syst. Des., 2000

Optimizing sequential verification by retiming transformations.

[BibT_eX]

[DOI]

Fabio Somenzi

Proceedings of the 37th Conference on Design Automation, 2000

1999

Improving the efficiency of BDD-based operators by means of partitioning.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

Computing Timed Transition Relations for Sequential Cycle-Based Simulation.

[BibT_eX]

[DOI]

Proceedings of the 1999 Design, 1999

Improving Symbolic Traversals by Means of Activity Profiles.

[BibT_eX]

[DOI]

Proceedings of the 36th Conference on Design Automation, 1999

Cycle-Based Symbolic Simulation of Gate-Level Synchronous Circuits.

[BibT_eX]

[DOI]

Valeria Bertacco

Maurizio Damiani

Proceedings of the 36th Conference on Design Automation, 1999

1998

Binary Decision Diagrams and the Multiple Variable Order Problem

[BibT_eX]

Universität Trier, Mathematik/Informatik, Forschungsbericht, 1998

Power optimization of core-based systems by address bus encoding.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 1998

Auxiliary variables for BDD-based representation and manipulation of Boolean functions.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 1998

Memory Optimization in Function and Set Manipulation with BDDs.

[BibT_eX]

[DOI]

Softw. Pract. Exp., 1998

1997

System-level power optimization of special purpose applications: the beach solution.

[BibT_eX]

[DOI]

Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997

Verification and synthesis of counters based on symbolic techniques.

[BibT_eX]

[DOI]

Proceedings of the European Design and Test Conference, 1997

Disjunctive Partitioning and Partial Iterative Squaring: An Effective Approach for Symbolic Traversal of Large Circuits.

[BibT_eX]

[DOI]

Proceedings of the 34st Conference on Design Automation, 1997

A parallel approach to symbolic traversal based on set partitioning.

[BibT_eX]

Proceedings of the Advances in Hardware Design and Verification, 1997

1996

Enhancing FSM Traversal by Temporary Re-Encoding.

[BibT_eX]

[DOI]

Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996

Improved reachability analysis of large finite state machines.

[BibT_eX]

[DOI]

Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

Decomposed symbolic forward traversals of large finite state machines.

[BibT_eX]

[DOI]

Proceedings of the conference on European design automation, 1996

Incremental re-encoding for symbolic traversal of product machines.

[BibT_eX]

[DOI]

Proceedings of the conference on European design automation, 1996

1995

Computing subsets of equivalence classes for large FSMs.

[BibT_eX]

[DOI]

Proceedings of the Proceedings EURO-DAC'95, 1995

Transforming boolean relations by symbolic encoding.

[BibT_eX]

[DOI]

Proceedings of the Correct Hardware Design and Verification Methods, 1995

1994

Full-Symbolic ATPG for Large Circuits.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 1994, 1994

Detecting hard faults with combined approximate forward/backward symbolic techniques.

[BibT_eX]

[DOI]

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

Efficient State Space Pruning in Symbolic Backward Traversal.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

Symbolic traversals of data paths with auxiliary variables.

[BibT_eX]

[DOI]

Proceedings of the Fourth Great Lakes Symposium on Design Automation of High Performance VLSI Systems, 1994

Symbolic exploration of large circuits with enhanced forward/backward traversals.

[BibT_eX]

[DOI]

Proceedings of the Proceedings EURO-DAC'94, 1994

Auxiliary Variables for Extending Symbolic Traversal Techniques to Data Paths.

[BibT_eX]

[DOI]