David Garrett

Orcid: 0000-0003-3827-5176

According to our database1, David Garrett authored at least 21 papers between 1997 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
A 1mW Always-on Computer Vision Deep Learning Neural Decision Processor.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023

2017
Recap of the 2017 International Symposium on Low Power Electronics and Design (ISLPED).
IEEE Des. Test, 2017

Message from the general co-chairs.
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017

2014

2012
Activity and environment classification using foot mounted navigation sensors.
Proceedings of the 2012 International Conference on Indoor Positioning and Indoor Navigation, 2012

2005
A 28.8 Mb/s 4 × 4 MIMO 3G CDMA receiver for frequency selective channels.
IEEE J. Solid State Circuits, 2005

2004
An eight-user UMTS channel unit Processor for 3GPP base station applications.
IEEE J. Solid State Circuits, 2004

Silicon complexity for maximum likelihood MIMO detection using spherical decoding.
IEEE J. Solid State Circuits, 2004

Non-Manhattan maze routing.
Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, 2004

2003
Integrated circuits for channel coding in 3G cellular mobile wireless systems.
IEEE Commun. Mag., 2003

Matrix datapath architecture for an iterative 4x4 MIMO noise whitening algorithm.
Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003


APP processing for high performance MIMO systems [receiver symbol detector].
Proceedings of the IEEE Custom Integrated Circuits Conference, 2003

2002
A unified turbo/Viterbi channel decoder for 3GPP mobile wireless in 0.18-μm CMOS.
IEEE J. Solid State Circuits, 2002

A low power normalized-LMS decision feedback equalizer for a wireless packet modem.
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

2001
Low Power Design for ASIC Cores.
VLSI Design, 2001

Energy efficient turbo decoding for 3G mobile.
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

A 2.5 Mb/s, 23 mW SOVA traceback chip for turbo decoding applications.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

1999
Challenges in clockgating for a low power ASIC methodology.
Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999

1998
Low power architecture of the soft-output Viterbi algorithm.
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998

1997
Power reduction techniques for a spread spectrum based correlator.
Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997


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