Fatih Hamzaoglu
According to our database1,
Fatih Hamzaoglu
authored at least 35 papers
between 2002 and 2022.
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Bibliography
2022
Gain-Cell CIM: Leakage and Bitline Swing Aware 2T1C Gain-Cell eDRAM Compute in Memory Design with Bitline Precharge DACs and Compact Schmitt Trigger ADCs.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
2021
IEEE Micro, 2021
16.2 eDRAM-CIM: Compute-In-Memory Design with Reconfigurable Embedded-Dynamic-Memory Array Realizing Adaptive Data Converters and Charge-Domain Computing.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
2019
Embedded Memories for Silicon-In-Package: Optimization of Memory Subsystem from IoT to Machine Learning.
Proceedings of the International Symposium on VLSI Design, Automation and Test, 2019
A 7Mb STT-MRAM in 22FFL FinFET Technology with 4ns Read Sensing Time at 0.9V Using Write-Verify-Write Scheme and Offset-Cancellation Sensing Technique.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
A 3.6Mb 10.1Mb/mm<sup>2</sup> Embedded Non-Volatile ReRAM Macro in 22nm FinFET Technology with Adaptive Forming/Set/Reset Schemes Yielding Down to 0.5V with Sensing Time of 5ns at 0.7V.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
Proceedings of the IEEE International Reliability Physics Symposium, 2019
2018
Session 31 overview: Computation in memory for machine learning: Technology directions and memory subcommittees.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
2017
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
An offset-cancelling four-phase voltage sense amplifier for resistive memories in 14nm CMOS.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017
2015
IEEE J. Solid State Circuits, 2015
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
2014
2<sup>nd</sup> generation embedded DRAM with 4X lower self refresh power in 22nm Tri-Gate CMOS technology.
Proceedings of the Symposium on VLSI Circuits, 2014
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
2013
A 4.6 GHz 162 Mb SRAM Design in 22 nm Tri-Gate CMOS Technology With Integrated Read and Write Assist Circuitry.
IEEE J. Solid State Circuits, 2013
2012
A 4.6GHz 162Mb SRAM design in 22nm tri-gate CMOS technology with integrated active VMIN-enhancing assist circuitry.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
2011
A 32 nm High-k Metal Gate SRAM With Adaptive Dynamic Stability Enhancement for Low-Voltage Operation.
IEEE J. Solid State Circuits, 2011
IEEE Des. Test Comput., 2011
2010
A 4.0 GHz 291 Mb Voltage-Scalable SRAM Design in a 32 nm High-k + Metal-Gate CMOS Technology With Integrated Power Management.
IEEE J. Solid State Circuits, 2010
IEEE J. Solid State Circuits, 2010
A 32nm High-k metal gate SRAM with adaptive dynamic stability enhancement for low-voltage operation.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
2009
Process, Temperature, and Supply-Noise Tolerant 45nm Dense Cache Arrays With Diffusion-Notch-Free (DNF) 6T SRAM Cells and Dynamic Multi-Vcc Circuits.
IEEE J. Solid State Circuits, 2009
A 3.8 GHz 153 Mb SRAM Design With Dynamic Stability Enhancement and Leakage Reduction in 45 nm High-k Metal Gate CMOS Technology.
IEEE J. Solid State Circuits, 2009
A 4.0 GHz 291Mb voltage-scalable SRAM design in 32nm high-κ metal-gate CMOS with integrated power management.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
2008
A 1.1 GHz 12 µA/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications.
IEEE J. Solid State Circuits, 2008
A 153Mb-SRAM Design with Dynamic Stability Enhancement and Leakage Reduction in 45nm High-Κ Metal-Gate CMOS Technology.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
2007
A 256-Kb Dual-V<sub>CC</sub> SRAM Building Block in 65-nm CMOS Process With Actively Clamped Sleep Transistor.
IEEE J. Solid State Circuits, 2007
A 1.1GHz 12μA/Mb-Leakage SRAM Design in 65nm Ultra-Low-Power CMOS with Integrated Leakage Reduction for Mobile Applications.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
2006
A 3-GHz 70-mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply.
IEEE J. Solid State Circuits, 2006
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
2005
SRAM design on 65-nm CMOS technology with dynamic sleep transistor for leakage reduction.
IEEE J. Solid State Circuits, 2005
2004
Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, 2004
2002
Analysis of dual-V<sub>T</sub> SRAM cells with full-swing single-ended bit line sensing for on-chip cache.
IEEE Trans. Very Large Scale Integr. Syst., 2002
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002