Seongjong Kim

According to our database1, Seongjong Kim authored at least 20 papers between 2013 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2020
A 617 TOPS/W All Digital Binary Neural Network Accelerator in 10nm FinFET CMOS.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020

25.9 Reconfigurable Transient Current-Mode Global Interconnect Circuits in 10nm CMOS for High-Performance Processors with Wide Voltage-Frequency Operating Range.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2019
A Near-Threshold Spiking Neural Network Accelerator With a Body-Swapping-Based In Situ Error Detection and Correction Technique.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Optimized Fused Floating-Point Many-Term Dot-Product Hardware for Machine Learning Accelerators.
Proceedings of the 26th IEEE Symposium on Computer Arithmetic, 2019

2017
In Situ Error Detection Techniques in Ultralow Voltage Pipelines: Analysis and Optimizations.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Near- and Sub-V<sub>t</sub> Pipelines Based on Wide-Pulsed-Latch Design Techniques.
IEEE J. Solid State Circuits, 2017

Compact and voltage-scalable sensor for accurate thermal sensing in dynamic thermal management.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

Near-Vt adaptive microprocessor and power-management-unit system based on direct error regulation.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017

2016
A 450mV timing-margin-free waveform sorter based on body swapping error correction.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

1.74-µW/ch, 95.3%-accurate spike-sorting hardware based on Bayesian decision.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

A 0.35V 1.3pJ/cycle 20MHz 8-bit 8-tap FIR core based on wide-pulsed-latch pipelines.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2015
Compact and Supply-Voltage-Scalable Temperature Sensors for Dense On-Chip Thermal Monitoring.
IEEE J. Solid State Circuits, 2015

Variation-Tolerant, Ultra-Low-Voltage Microprocessor With a Low-Overhead, Within-a-Cycle In-Situ Timing-Error Detection and Correction Technique.
IEEE J. Solid State Circuits, 2015

A 30.1μm<sup>2</sup>, > ±1.1°C-3σ-error, 0.4-to-1.0V temperature sensor based on direct threshold-voltage sensing for on-chip dense thermal monitoring.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

2014
Razor-Lite: A Light-Weight Register for Error Detection by Observing Virtual Supply Rails.
IEEE J. Solid State Circuits, 2014

R-processor: 0.4V resilient processor with a voltage-scalable and low-overhead in-situ error detection and correction technique in 65nm CMOS.
Proceedings of the Symposium on VLSI Circuits, 2014

16.4 0.6-to-1.0V 279μm<sup>2</sup>, 0.92μW temperature sensor with less than +3.2/-3.4°C error for on-chip dense thermal monitoring.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

Analysis and optimization of in-situ error detection techniques in ultra-low-voltage pipeline.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014

Reconfigurable regenerator-based interconnect design for ultra-dynamic-voltage-scaling systems.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014

2013
Razor-lite: A side-channel error-detection register for timing-margin recovery in 45nm SOI CMOS.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013


  Loading...