David T. Miller

According to our database1, David T. Miller authored at least 10 papers between 1984 and 1992.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

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Bibliography

1992
Dynamic redundancy identification in automatic test generation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

Freeze!: A New Approach for Testing Sequential Circuits.
Proceedings of the 29th Design Automation Conference, 1992

1990
Global cost functions for test generation.
Proceedings of the Proceedings IEEE International Test Conference 1990, 1990

1989
System-level design verification in the AT&T Computer Division: tools.
Proceedings of the Computer Design: VLSI in Computers and Processors, 1989

System-level design verification in the AT&T computer division: overview and strategy.
Proceedings of the Computer Design: VLSI in Computers and Processors, 1989

1986
Checkpoint Faults are not Sufficient Target Faults for Test Generation.
IEEE Trans. Computers, 1986

SMART and FAST: Test Generation for VLSI Scan-Design Circuits.
IEEE Des. Test, 1986

1985
Test Generation In Lamp2: Concepts and Algorithms.
Proceedings of the Proceedings International Test Conference 1985, 1985

Test Generation In Lamp2: System Overview.
Proceedings of the Proceedings International Test Conference 1985, 1985

1984
Critical Path Tracing: An Alternative to Fault Simulation.
IEEE Des. Test, 1984


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