Davide Tasca

According to our database, Davide Tasca authored at least 8 papers between 2009 and 2012.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2012

Low-power low-jitter fractional-N frequency synthesizer using bang bang phase detection.

Davide Tasca

PhD thesis, 2012

2011

Low-Power Divider Retiming in a 3-4 GHz Fractional-N PLL.

Davide Tasca, Marco Zanuso, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita

IEEE Trans. Circuits Syst. II Express Briefs, 2011

A 2.9-4.0-GHz Fractional-N Digital PLL With Bang-Bang Phase Detector and 560-fs_rms Integrated Jitter at 4.5-mW Power.

Davide Tasca, Marco Zanuso, Giovanni Marzin, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita

IEEE J. Solid State Circuits, 2011

A 2.9-to-4.0GHz fractional-N digital PLL with bang-bang phase detector and 560fsrms integrated jitter at 4.5mW power.

Davide Tasca, Marco Zanuso, Giovanni Marzin, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita

Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2010

AD-PLL for WiMAX with Digitally-Regulated TDC and Glitch Correction Logic.

Salvatore Levantino, Marco Zanuso, Paolo Madoglio, Davide Tasca, Carlo Samori, Andrea L. Lacaita

EURASIP J. Embed. Syst., 2010

2009

Noise Analysis and Minimization in Bang-Bang Digital PLLs.

Marco Zanuso, Davide Tasca, Salvatore Levantino, Andrea Donadel, Carlo Samori, Andrea L. Lacaita

IEEE Trans. Circuits Syst. II Express Briefs, 2009

A glitch-corrector circuit for low-spur ADPLLs.

Marco Zanuso, Salvatore Levantino, Davide Tasca, Daniele Raiteri, Carlo Samori, Andrea L. Lacaita

Proceedings of the 16th IEEE International Conference on Electronics, 2009

An all-digital architecture for low-jitter regulated delay lines.

Salvatore Levantino, Marco Zanuso, Davide Tasca, Carlo Samori, Andrea L. Lacaita

Proceedings of the 16th IEEE International Conference on Electronics, 2009