Carlo Samori

Proceedings of the IEEE International Solid-State Circuits Conference, 2024

10.1 An 8.75GHz Fractional-N Digital PLL with a Reverse-Concavity Variable-Slope DTC Achieving 57.3fsrms Integrated Jitter and -252.4dB FoM.

[BibT_eX]

[DOI]

Michele Rossoni

Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2023

A Low-Spur and Low-Jitter Fractional-N Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, December, 2023

A Novel LO Phase-Shifting System Based on Digital Bang-Bang PLLs With Background Phase-Offset Correction for Integrated Phased Arrays.

[BibT_eX]

[DOI]

Francesco Tesolin

IEEE J. Solid State Circuits, September, 2023

A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner.

[BibT_eX]

[DOI]

Francesco Buccoleri

IEEE J. Solid State Circuits, March, 2023

A 2GS/s 11b 8x Interleaved ADC with 9.2 ENOB and 69.9dB SFDR in 28nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

A 76.7fs-lntegrated-Jitter and -71.9dBc In-Band Fractional-Spur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid- State Circuits Conference, 2023

A 9.25GHz Digital PLL with Fractional-Spur Cancellation Based on a Multi-DTC Topology.

[BibT_eX]

[DOI]

Giacomo Castoro

Proceedings of the IEEE International Solid- State Circuits Conference, 2023

2022

A 900-MS/s SAR-Based Time-Interleaved ADC With a Fully Programmable Interleaving Factor and On-Chip Scalable Background Calibrations.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2022

Novel Feed-Forward Technique for Digital Bang-Bang PLL to Achieve Fast Lock and Low Phase Noise.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

A 12.5-GHz Fractional-N Type-I Sampling PLL Achieving 58-fs Integrated Jitter.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2022

A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2022

A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking-Time.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2022

A 10.2-ENOB, 150-MS/s Redundant SAR ADC With a Quasi-Monotonic Switching Algorithm for Time-Interleaved Converters.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE Interregional NEWCAS Conference, 2022

A 68.6fsrms-Total-integrated-Jitter and 1.5µs-LocKing-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2022

Concurrent Effect of Redundancy and Switching Algorithms in SAR ADCs.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler.

[BibT_eX]

[DOI]

Francesco Buccoleri

Proceedings of the IEEE Custom Integrated Circuits Conference, 2022

2021

A Novel Topology of Coupled Phase-Locked Loops.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

A Comprehensive Phase Noise Analysis of Bang-Bang Digital PLLs.

[BibT_eX]

[DOI]

Luca Avallone

Mario Mercandelli

Alessio Santiccioli

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

32.8 A 98.4fs-Jitter 12.9-to-15.1GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays.

[BibT_eX]

[DOI]

Alessio Santiccioli

Mario Mercandelli

Proceedings of the IEEE International Solid-State Circuits Conference, 2021

A 12.9-to-15.1GHz Digital PLL Based on a Bang-Bang Phase Detector with Adaptively Optimized Noise Shaping Achieving 107.6fs Integrated Jitter.

[BibT_eX]

[DOI]

Mario Mercandelli

Alessio Santiccioli

Proceedings of the IEEE International Solid-State Circuits Conference, 2021

A PLL-Based Digital Technique for Orthogonal Correction of ADC Non-Linearity.

[BibT_eX]

[DOI]

Proceedings of the 28th IEEE International Conference on Electronics, 2021

Digital PLLs: the modern timing reference for radar and communication systems.

[BibT_eX]

[DOI]

Luca Bertulessi

Proceedings of the 47th ESSCIRC 2021, 2021

A 3.7-to-4.1GHz Narrowband Digital Bang-Bang PLL with a Multitaps LMS Algorithm to Automatically Control the Bandwidth Achieving 183fs Integrated Jitter.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021

2020

Jitter Minimization in Digital PLLs with Mid-Rise TDCs.

[BibT_eX]

[DOI]

Luca Avallone

Saleh Karman

IEEE Trans. Circuits Syst. I Regul. Pap., 2020

A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-N Bang-Bang PLL With Digital Frequency-Error Recovery for Fast Locking.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2020

17.2 A 66fsrmsJitter 12.8-to-15.2GHz Fractional-N Bang-Bang PLL with Digital Frequency-Error Recovery for Fast Locking.

[BibT_eX]

[DOI]

Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

17.5 A 12.5GHz Fractional-N Type-I Sampling PLL Achieving 58fs Integrated Jitter.

[BibT_eX]

[DOI]

Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2019

Time-Variant Modeling and Analysis of Multiplying Delay-Locked Loops.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

A 1.6-to-3.0-GHz Fractional-N MDLL With a Digital-to-Time Converter Range-Reduction Technique Achieving 397-fs Jitter at 2.5-mW Power.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2019

A 30-GHz Digital Sub-Sampling Fractional- $N$ PLL With -238.6-dB Jitter-Power Figure of Merit in 65-nm LP CMOS.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2019

A 30GHz Digital Sub-Sampling Fractional-N PLL with 198fsrms Jitter in 65nm LP CMOS.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid- State Circuits Conference, 2019

A 1.6-to-3.0-GHz Fractional-N MDLL with a Digital-to-Time Converter Range-Reduction Technique Achieving 397fs Jitter at 2.5-mW Power.

[BibT_eX]

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

Digitally-Intensive Fast Frequency Modulators for FMCW Radars in CMOS : (Invited Paper).

[BibT_eX]

[DOI]

Dmytro Cherniak

Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

2018

PLL-Based Wideband Frequency Modulator: Two-Point Injection Versus Pre-Emphasis Technique.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2018

A Background Calibration Technique to Control the Bandwidth of Digital PLLs.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2018

A 23-GHz Low-Phase-Noise Digital Bang-Bang PLL for Fast Triangular and Sawtooth Chirp Modulation.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2018

A 23GHz low-phase-noise digital bang-bang PLL for fast triangular and saw-tooth chirp modulation.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

A low-phase-noise digital bang-bang PLL with fast lock over a wide lock range.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

A Novel LMS-Based Calibration Scheme for Fractional-N Digital PLLs.

[BibT_eX]

[DOI]

Tuan Minh Vo

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Impact of CMOS Scaling on Switched-Capacitor Power Amplifiers.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Adaptive Digital Pre-Emphasis for PLL-Based FMCW Modulators.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017

A novel segmentation scheme for DTC-based ΔΣ fractional-N PLL.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Analysis of millimeter-wave digital frequency modulators for ubiquitous sensors and radars.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2015

A 1.7 GHz Fractional-N Frequency Synthesizer Based on a Multiplying Delay-Locked Loop.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2015

EP2: Lost art? Analog tricks and techniques from the masters.

[BibT_eX]

[DOI]

Tsung-Hsien Lin

Richard Schreier

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2014

Analysis and Design of Low-Jitter Digital Bang-Bang Phase-Locked Loops.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Introduction to the Special Issue on the 2014 IEEE International Solid-State Circuits Conference (ISSCC).

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2014

An Adaptive Pre-Distortion Technique to Mitigate the DTC Nonlinearity in Digital PLLs.

[BibT_eX]

[DOI]

Giovanni Marzin

IEEE J. Solid State Circuits, 2014

2.9 A Background calibration technique to control bandwidth in digital PLLs.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

21.1 A 1.7GHz MDLL-based fractional-N frequency synthesizer with 1.4ps RMS integrated jitter and 3mW power using a 1b TDC.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2013

Exploiting Stochastic Resonance to Enhance the Performance of Digital Bang-Bang PLLs.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2013

Suppression of Flicker Noise Up-Conversion in a 65-nm CMOS VCO in the 3.0-to-3.6 GHz Band.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2013

A Wideband Fractional-N PLL With Suppressed Charge-Pump Noise and Automatic Loop Filter Calibration.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2013

Simulating phase noise induced from cyclostationary noise sources.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

A spur cancellation technique for MDLL-based frequency synthesizers.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

An efficient method to compute phase-noise in injection-locked frequency dividers.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Minimum-jitter design of bang-bang PLLs in the presence of 1/f2 and 1/f3 DCO noise.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Background adaptive linearization of high-speed digital-to-analog Converters.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Nonlinearity cancellation in digital PLLs (Invited paper).

[BibT_eX]

[DOI]

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2012

Efficient Calculation of the Impulse Sensitivity Function in Oscillators.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2012

Flicker Noise Up-Conversion due to Harmonic Distortion in Van der Pol CMOS Oscillators.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2012

A 20 Mb/s Phase Modulator Based on a 3.6 GHz Digital PLL With -36 dB EVM at 5 mW Power.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2012

A 20Mb/s phase modulator based on a 3.6GHz digital PLL with -36dB EVM at 5mW power.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2011

Low-Power Divider Retiming in a 3-4 GHz Fractional-N PLL.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2011

A Wideband 3.6 GHz Digital ΔΣ Fractional-N PLL With Phase Interpolation Divider and Digital Spur Cancellation.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2011

A 2.9-4.0-GHz Fractional-N Digital PLL With Bang-Bang Phase Detector and 560-fsrms Integrated Jitter at 4.5-mW Power.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2011

A 2.9-to-4.0GHz fractional-N digital PLL with bang-bang phase detector and 560fsrms integrated jitter at 4.5mW power.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2011

Multipath adaptive cancellation of divider non-linearity in fractional-N PLLs.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Behavioral phase-noise analysis of charge-pump phase-locked loops.

[BibT_eX]

[DOI]

Proceedings of the 20th European Conference on Circuit Theory and Design, 2011

2010

Time-to-Digital Converter for Frequency Synthesis Based on a Digital Bang-Bang DLL.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2010

Folding of Phase Noise Spectra in Charge-Pump Phase-Locked Loops Induced by Frequency Division.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2010

AD-PLL for WiMAX with Digitally-Regulated TDC and Glitch Correction Logic.

[BibT_eX]

[DOI]

EURASIP J. Embed. Syst., 2010

A 3MHz-BW 3.6GHz digital fractional-N PLL with sub-gate-delay TDC, phase-interpolation divider, and digital mismatch cancellation.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

Suppression of flicker noise upconversion in a 65nm CMOS VCO in the 3.0-to-3.6GHz band.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

Time-to-digital converter with 3-ps resolution and digital linearization algorithm.

[BibT_eX]

[DOI]

Proceedings of the 36th European Solid-State Circuits Conference, 2010

2009

Noise Analysis and Minimization in Bang-Bang Digital PLLs.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2009

A glitch-corrector circuit for low-spur ADPLLs.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International Conference on Electronics, 2009

An all-digital architecture for low-jitter regulated delay lines.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International Conference on Electronics, 2009

2008

Analysis and Characterization of the Effects of Clock Jitter in A/D Converters for Subsampling.

[BibT_eX]

[DOI]

Alfio Zanchi

IEEE Trans. Circuits Syst. I Regul. Pap., 2008

Low-Power Signal Component Separator for a 64-QAM 802.11 LINC Transmitter.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2008

A 2.5-GHz DDFS-PLL With 1.8-MHz Bandwidth in 0.35-µm CMOS.

[BibT_eX]

[DOI]

Antonio G. M. Strollo

IEEE J. Solid State Circuits, 2008

2007

Quantization Effects in All-Digital Phase-Locked Loops.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2007

A multistandard Σ-Δ fractional-N frequency synthesizer for 802.11a/b/g WLAN.

[BibT_eX]

[DOI]

Andrea Bonfanti

Andrea L. Lacaita

Proceedings of the 33rd European Solid-State Circuits Conference, 2007

2006

Matching requirements in LINC transmitters for OFDM signals.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2006

Multiphase LC oscillators.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2006

A varactor configuration minimizing the amplitude-to-phase noise conversion in VCOs.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2006

5-GHz Oscillator Array With Reduced Flicker Up-Conversion in 0.13-$muhboxm$CMOS.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2006

Low-power CMOS IEEE 802.11a/g Signal Separator for Outphasing Transmitter.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

2004

Fast-switching analog PLL with finite-impulse response.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2004

A 13.5-mW 5-GHz frequency synthesizer with dynamic-logic frequency divider.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2004

Phase noise in digital frequency dividers.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2004

Phase noise and accuracy in quadrature oscillators.

[BibT_eX]

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Fast-switching analog PLL with finite-impulse response.

[BibT_eX]

[DOI]

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A multi-tank LC-oscillator [microwave oscillator example].

[BibT_eX]

[DOI]

Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004

Differential tuning oscillators with reduced flicker noise upconversion.

[BibT_eX]

[DOI]

Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004

5-GHz in-phase coupled oscillators with 39% tuning range.

[BibT_eX]

[DOI]

Luca Romanò

Vita Minerva

Silvia Cavalieri d'Oro

Marco Politi

Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

2003

A DDS-based PLL for 2.4-GHz frequency synthesis.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2003

A CMOS GSM IF-sampling circuit with reduced in-channel aliasing.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2003

A low-phase-noise 5-GHz CMOS quadrature VCO using superharmonic coupling.

[BibT_eX]

[DOI]

Sander L. J. Gierkink

IEEE J. Solid State Circuits, 2003

A voltage-controlled oscillator for IEEE 802.11a and HiperLAN2 application.

[BibT_eX]

[DOI]

Andrea Giovanni Bonfanti

Proceedings of the ESSCIRC 2003, 2003

2002

Frequency dependence on bias current in 5 GHz CMOS VCOs: impact on tuning range and flicker noise upconversion.

[BibT_eX]

[DOI]

Andrea Bonfanti

Sander L. J. Gierkink

Andrea L. Lacaita

Vito Boccuzzi

IEEE J. Solid State Circuits, 2002

Analysis and design of a 1.8-GHz CMOS LC quadrature VCO.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2002

Integrated LC oscillators for frequency synthesis in wireless applications.

[BibT_eX]

[DOI]

Andrea L. Lacaita

IEEE Commun. Mag., 2002

2001

A 2-V 2.5-GHz-104-dBc/Hz at 100 kHz fully integrated VCO with wide-band low-noise automatic amplitude control loop.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2001

Automatic amplitude control loop for a 2-V, 2.5-GHz LC-tank VCO.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001

A -94 dBc/Hz@100 kHz, fully-integrated, 5-GHz, CMOS VCO with 18% tuning range for Bluetooth applications.

[BibT_eX]

[DOI]