Carlo Samori

According to our database1, Carlo Samori authored at least 72 papers between 1998 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Awards

IEEE Fellow

IEEE Fellow 2017, "For contributions to design of integrated Voltage Controlled Oscillators and Phase-Locked Loops".

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2020
Jitter Minimization in Digital PLLs with Mid-Rise TDCs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020

A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-N Bang-Bang PLL With Digital Frequency-Error Recovery for Fast Locking.
IEEE J. Solid State Circuits, 2020

17.2 A 66fsrmsJitter 12.8-to-15.2GHz Fractional-N Bang-Bang PLL with Digital Frequency-Error Recovery for Fast Locking.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

17.5 A 12.5GHz Fractional-N Type-I Sampling PLL Achieving 58fs Integrated Jitter.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2019
Time-Variant Modeling and Analysis of Multiplying Delay-Locked Loops.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

A 1.6-to-3.0-GHz Fractional-N MDLL With a Digital-to-Time Converter Range-Reduction Technique Achieving 397-fs Jitter at 2.5-mW Power.
IEEE J. Solid State Circuits, 2019

A 30-GHz Digital Sub-Sampling Fractional- $N$ PLL With -238.6-dB Jitter-Power Figure of Merit in 65-nm LP CMOS.
IEEE J. Solid State Circuits, 2019

A 30GHz Digital Sub-Sampling Fractional-N PLL with 198fsrms Jitter in 65nm LP CMOS.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

A 1.6-to-3.0-GHz Fractional-N MDLL with a Digital-to-Time Converter Range-Reduction Technique Achieving 397fs Jitter at 2.5-mW Power.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

Digitally-Intensive Fast Frequency Modulators for FMCW Radars in CMOS : (Invited Paper).
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

2018
PLL-Based Wideband Frequency Modulator: Two-Point Injection Versus Pre-Emphasis Technique.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

A Background Calibration Technique to Control the Bandwidth of Digital PLLs.
IEEE J. Solid State Circuits, 2018

A 23-GHz Low-Phase-Noise Digital Bang-Bang PLL for Fast Triangular and Sawtooth Chirp Modulation.
IEEE J. Solid State Circuits, 2018

A 23GHz low-phase-noise digital bang-bang PLL for fast triangular and saw-tooth chirp modulation.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

A low-phase-noise digital bang-bang PLL with fast lock over a wide lock range.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

A Novel LMS-Based Calibration Scheme for Fractional-N Digital PLLs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Impact of CMOS Scaling on Switched-Capacitor Power Amplifiers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Adaptive Digital Pre-Emphasis for PLL-Based FMCW Modulators.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017
A novel segmentation scheme for DTC-based ΔΣ fractional-N PLL.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Analysis of millimeter-wave digital frequency modulators for ubiquitous sensors and radars.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2015
A 1.7 GHz Fractional-N Frequency Synthesizer Based on a Multiplying Delay-Locked Loop.
IEEE J. Solid State Circuits, 2015

EP2: Lost art? Analog tricks and techniques from the masters.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2014
Analysis and Design of Low-Jitter Digital Bang-Bang Phase-Locked Loops.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Introduction to the Special Issue on the 2014 IEEE International Solid-State Circuits Conference (ISSCC).
IEEE J. Solid State Circuits, 2014

An Adaptive Pre-Distortion Technique to Mitigate the DTC Nonlinearity in Digital PLLs.
IEEE J. Solid State Circuits, 2014

2.9 A Background calibration technique to control bandwidth in digital PLLs.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

21.1 A 1.7GHz MDLL-based fractional-N frequency synthesizer with 1.4ps RMS integrated jitter and 3mW power using a 1b TDC.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2013
Exploiting Stochastic Resonance to Enhance the Performance of Digital Bang-Bang PLLs.
IEEE Trans. Circuits Syst. II Express Briefs, 2013

Suppression of Flicker Noise Up-Conversion in a 65-nm CMOS VCO in the 3.0-to-3.6 GHz Band.
IEEE J. Solid State Circuits, 2013

A Wideband Fractional-N PLL With Suppressed Charge-Pump Noise and Automatic Loop Filter Calibration.
IEEE J. Solid State Circuits, 2013

Simulating phase noise induced from cyclostationary noise sources.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

A spur cancellation technique for MDLL-based frequency synthesizers.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

An efficient method to compute phase-noise in injection-locked frequency dividers.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Minimum-jitter design of bang-bang PLLs in the presence of 1/f<sup>2</sup> and 1/f<sup>3</sup> DCO noise.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Background adaptive linearization of high-speed digital-to-analog Converters.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Nonlinearity cancellation in digital PLLs (Invited paper).
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2012
Efficient Calculation of the Impulse Sensitivity Function in Oscillators.
IEEE Trans. Circuits Syst. II Express Briefs, 2012

Flicker Noise Up-Conversion due to Harmonic Distortion in Van der Pol CMOS Oscillators.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012

A 20 Mb/s Phase Modulator Based on a 3.6 GHz Digital PLL With -36 dB EVM at 5 mW Power.
IEEE J. Solid State Circuits, 2012

A 20Mb/s phase modulator based on a 3.6GHz digital PLL with -36dB EVM at 5mW power.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2011
Low-Power Divider Retiming in a 3-4 GHz Fractional-N PLL.
IEEE Trans. Circuits Syst. II Express Briefs, 2011

A Wideband 3.6 GHz Digital ΔΣ Fractional-N PLL With Phase Interpolation Divider and Digital Spur Cancellation.
IEEE J. Solid State Circuits, 2011

A 2.9-4.0-GHz Fractional-N Digital PLL With Bang-Bang Phase Detector and 560-fs<sub>rms</sub> Integrated Jitter at 4.5-mW Power.
IEEE J. Solid State Circuits, 2011

A 2.9-to-4.0GHz fractional-N digital PLL with bang-bang phase detector and 560fsrms integrated jitter at 4.5mW power.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

Multipath adaptive cancellation of divider non-linearity in fractional-N PLLs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Behavioral phase-noise analysis of charge-pump phase-locked loops.
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011

2010
Time-to-Digital Converter for Frequency Synthesis Based on a Digital Bang-Bang DLL.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010

Folding of Phase Noise Spectra in Charge-Pump Phase-Locked Loops Induced by Frequency Division.
IEEE Trans. Circuits Syst. II Express Briefs, 2010

AD-PLL for WiMAX with Digitally-Regulated TDC and Glitch Correction Logic.
EURASIP J. Embed. Syst., 2010

A 3MHz-BW 3.6GHz digital fractional-N PLL with sub-gate-delay TDC, phase-interpolation divider, and digital mismatch cancellation.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

Suppression of flicker noise upconversion in a 65nm CMOS VCO in the 3.0-to-3.6GHz band.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

Time-to-digital converter with 3-ps resolution and digital linearization algorithm.
Proceedings of the 36th European Solid-State Circuits Conference, 2010

2009
Noise Analysis and Minimization in Bang-Bang Digital PLLs.
IEEE Trans. Circuits Syst. II Express Briefs, 2009

A glitch-corrector circuit for low-spur ADPLLs.
Proceedings of the 16th IEEE International Conference on Electronics, 2009

An all-digital architecture for low-jitter regulated delay lines.
Proceedings of the 16th IEEE International Conference on Electronics, 2009

2008
Analysis and Characterization of the Effects of Clock Jitter in A/D Converters for Subsampling.
IEEE Trans. Circuits Syst. I Regul. Pap., 2008

Low-Power Signal Component Separator for a 64-QAM 802.11 LINC Transmitter.
IEEE J. Solid State Circuits, 2008

A 2.5-GHz DDFS-PLL With 1.8-MHz Bandwidth in 0.35-µm CMOS.
IEEE J. Solid State Circuits, 2008

2007
Quantization Effects in All-Digital Phase-Locked Loops.
IEEE Trans. Circuits Syst. II Express Briefs, 2007

2006
Matching requirements in LINC transmitters for OFDM signals.
IEEE Trans. Circuits Syst. I Regul. Pap., 2006

Multiphase LC oscillators.
IEEE Trans. Circuits Syst. I Regul. Pap., 2006

A varactor configuration minimizing the amplitude-to-phase noise conversion in VCOs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2006

Low-power CMOS IEEE 802.11a/g Signal Separator for Outphasing Transmitter.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

2004
Fast-switching analog PLL with finite-impulse response.
IEEE Trans. Circuits Syst. I Regul. Pap., 2004

Phase noise and accuracy in quadrature oscillators.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Fast-switching analog PLL with finite-impulse response.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A multi-tank LC-oscillator [microwave oscillator example].
Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004

Differential tuning oscillators with reduced flicker noise upconversion.
Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004

5-GHz in-phase coupled oscillators with 39% tuning range.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

2000
An integrated active-quenching circuit for single-photon avalanche diodes.
IEEE Trans. Instrum. Meas., 2000

Fast simulation techniques for phase noise analysis of oscillators.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1998
Design Issues of LC Tuned Oscillators for Integrated Transceivers.
Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998


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