Giovanni Marzin

According to our database1, Giovanni Marzin authored at least 13 papers between 2011 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2020
Achieving Phase Coherency and Gain Stability in Active Antenna Arrays for Sub-6 GHz FDD and TDD FD-MIMO: Challenges and Solutions.
IEEE Access, 2020

2018
First Commercial Hybrid Massive MIMO System for Sub-6Hz Bands.
Proceedings of the IEEE 5G World Forum, 2018

2015
A 1.7 GHz Fractional-N Frequency Synthesizer Based on a Multiplying Delay-Locked Loop.
IEEE J. Solid State Circuits, 2015

2014
An Adaptive Pre-Distortion Technique to Mitigate the DTC Nonlinearity in Digital PLLs.
IEEE J. Solid State Circuits, 2014

2.9 A Background calibration technique to control bandwidth in digital PLLs.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

21.1 A 1.7GHz MDLL-based fractional-N frequency synthesizer with 1.4ps RMS integrated jitter and 3mW power using a 1b TDC.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2013
Design of a high efficiency wideband phase modulator for wireless systems.
PhD thesis, 2013

A Wideband Fractional-N PLL With Suppressed Charge-Pump Noise and Automatic Loop Filter Calibration.
IEEE J. Solid State Circuits, 2013

A spur cancellation technique for MDLL-based frequency synthesizers.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2012
A 20 Mb/s Phase Modulator Based on a 3.6 GHz Digital PLL With -36 dB EVM at 5 mW Power.
IEEE J. Solid State Circuits, 2012

A 20Mb/s phase modulator based on a 3.6GHz digital PLL with -36dB EVM at 5mW power.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2011
A 2.9-4.0-GHz Fractional-N Digital PLL With Bang-Bang Phase Detector and 560-fs<sub>rms</sub> Integrated Jitter at 4.5-mW Power.
IEEE J. Solid State Circuits, 2011

A 2.9-to-4.0GHz fractional-N digital PLL with bang-bang phase detector and 560fsrms integrated jitter at 4.5mW power.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011


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