Justin E. Harlow III

According to our database1, Justin E. Harlow III authored at least 11 papers between 1977 and 2007.

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Bibliography

2007
Architectures for Silicon Nanoelectronics and Beyond.
Computer, 2007

2006
A novel approach for variation aware power minimization during gate sizing.
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006

2003
Toward Design Technology in 2020: Trends, Issues, and Challenges.
Proceedings of the 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), 2003

2001
Design of experiments and evaluation of BDD ordering heuristics.
Int. J. Softw. Tools Technol. Transf., 2001

2000
Overview of Popular Benchmark Sets.
IEEE Des. Test Comput., 2000

Guest Editors' Introduction: Benchmarking for Design and Test.
IEEE Des. Test Comput., 2000

1999
Mirror, mirror, on the wall...is the new release any different at all? [BDDs].
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

1998
Design of experiments in BDD variable ordering: lessons learned.
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

Design of Experiments for Evaluation of BDD Packages Using Controlled Circuit Mutations.
Proceedings of the Formal Methods in Computer-Aided Design, 1998

Synthesis of Wiring Signature-Invariant Equivalence Class Circuit Mutants and Applications to Benchmarking.
Proceedings of the 1998 Design, 1998

1977
The open shop interactive mask design operation at harris semiconductor.
Proceedings of the 14th Design Automation Conference, 1977


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