Debasri Saha
Orcid: 0000-0002-7935-0980
According to our database1,
Debasri Saha
authored at least 51 papers
between 2006 and 2024.
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Bibliography
2024
Scalable Test Generation to Trigger Rare Targets in High-Level Synthesizable IPs for Cloud FPGAs.
CoRR, 2024
Proceedings of the International Symposium on Secure and Private Execution Environment Design, 2024
2023
AgEncID: Aggregate Encryption Individual Decryption of Key for FPGA Bitstream IP Cores in Cloud.
CoRR, 2023
2022
Quantum Inf. Process., 2022
Test Generation for SystemC designs by interlaced Greybox Fuzzing and Concolic Execution.
CoRR, 2022
GreyConE: Greybox Fuzzing + Concolic Execution Guided Test Generation for High Level Designs.
Proceedings of the IEEE International Test Conference, 2022
2021
Minimization of WCRT with Recovery Assurance from Hardware Trojans for Tasks on FPGA-based Cloud.
ACM Trans. Embed. Comput. Syst., 2021
Circuit Design for k-Coloring Problem and Its Implementation in Any Dimensional Quantum System.
SN Comput. Sci., 2021
FuCE: Fuzzing+Concolic Execution guided Trojan Detection in Synthesizable Hardware Designs.
CoRR, 2021
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2021
2020
Dynamic power-aware scheduling of real-time tasks for FPGA-based cyber physical systems against power draining hardware trojan attacks.
J. Supercomput., 2020
Asymptotically Improved Grover's Algorithm in any Dimensional Quantum System with Novel Decomposed n-qudit Toffoli Gate.
CoRR, 2020
Circuit Design for K-coloring Problem and it's Implementation on Near-term Quantum Devices.
CoRR, 2020
A Multi-Agent Co-operative Model to Facilitate Criticality based Reliability for Mixed Critical Task Execution on FPGA based Cloud Environment.
Proceedings of the 33rd International Conference on VLSI Design and 19th International Conference on Embedded Systems, 2020
Ensuring Green Computing in Reconfigurable Hardware based Cloud Platforms from Hardware Trojan Attacks.
Proceedings of the 2020 IEEE Region 10 Conference, 2020
Circuit Design for K-coloring Problem and its Implementation on Near-term Quantum Devices.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2020
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
2019
Guided GA-Based Multiobjective Optimization of Placement and Assignment of TSVs in 3-D ICs.
IEEE Trans. Very Large Scale Integr. Syst., 2019
Stigmergy-Based Security for SoC Operations From Runtime Performance Degradation of SoC Components.
ACM Trans. Embed. Comput. Syst., 2019
Criticality based reliability against hardware Trojan attacks for processing of tasks on reconfigurable hardware.
Microprocess. Microsystems, 2019
Microprocess. Microsystems, 2019
Proceedings of the TENCON 2019, 2019
2018
Proceedings of the VLSI Design and Test - 22nd International Symposium, 2018
Reliability Driven Mixed Critical Tasks Processing on FPGAs Against Hardware Trojan Attacks.
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018
Proceedings of the Advanced Computing and Systems for Security, 2018
2017
Microprocess. Microsystems, 2017
ACM J. Emerg. Technol. Comput. Syst., 2017
Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017
Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017
A CAD approach for on-chip PDN with power and supply noise reduction for multi-voltage SOCS in pre-layout stage.
Proceedings of the 7th International Symposium on Embedded Computing and System Design, 2017
Proceedings of the Computational Intelligence, Communications, and Business Analytics, 2017
2016
Embedding of signatures in reconfigurable scan architecture for authentication of intellectual properties in system-on-chip.
IET Comput. Digit. Tech., 2016
Pre-layout module wise decap allocation for noise suppression and accurate delay estimation of SoC.
Proceedings of the 20th International Symposium on VLSI Design and Test, 2016
2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
Pre-Layout Decoupling Capacitance Estimation and Allocation for Noise-Aware Crypto-System on Chip Applications.
J. Low Power Electron., 2015
RTNA: Securing SOC architectures from confidentiality attacks at runtime using ART1 neural networks.
Proceedings of the 19th International Symposium on VLSI Design and Test, 2015
Proceedings of the 4th International Conference on Frontiers in Intelligent Computing: Theory and Applications, 2015
2014
Proceedings of the 2014 International Conference on Advances in Computing, 2014
Analysis of Secret Key Revealing Trojan Using Path Delay Analysis for Some Cryptocores.
Proceedings of the 3rd International Conference on Frontiers of Intelligent Computing: Theory and Applications (FICTA) 2014, 2014
Proceedings of the 9th Workshop on Embedded Systems Security, 2014
2012
Secure Public Verification of IP Marks in FPGA Design Through a Zero-Knowledge Protocol.
IEEE Trans. Very Large Scale Integr. Syst., 2012
2011
VLSI Design, 2011
IET Comput. Digit. Tech., 2011
2010
IET Comput. Digit. Tech., 2010
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010
2009
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009
2008
Proceedings of the IEEE Reglon 10 Colloquium and Third International Conference on Industrial and Information Systems, 2008
2007
A Novel Scheme for Encoding and Watermark Embedding in VLSI Physical Design for IP Protection.
Proceedings of the 2007 International Conference on Computing: Theory and Applications (ICCTA 2007), 2007
Proceedings of the 10th International Conference on Information Technology, 2007
2006
A Mimetic Algorithm for Refinement of Lower Bound of Number of Tracks in Channel Routing Problem.
Proceedings of the Intelligent Information Processing III, 2006