Susmita Sur-Kolay

According to our database1, Susmita Sur-Kolay authored at least 92 papers between 1988 and 2019.

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Bibliography

2019
Guided GA-Based Multiobjective Optimization of Placement and Assignment of TSVs in 3-D ICs.
IEEE Trans. VLSI Syst., 2019

Selective Sensitization of Useless Sneak-Paths for Test Optimization in Memristor-Arrays.
Proceedings of the 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems, 2019

Minimization of Flare in EUVL by Simultaneous Wire Segment Perturbation and Dummification.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

Fault Coverage of a Test Set on Structure-Preserving Siblings of a Circuit-Under-Test.
Proceedings of the 28th IEEE Asian Test Symposium, 2019

2018
Exploring the Scope of Unconstrained Via Minimization by Recursive Floorplan Bipartitioning.
CoRR, 2018

Early Routability Assessment in VLSI Floorplans: A Generalized Routing Model.
CoRR, 2018

STAIRoute: Early Global Routing using Monotone Staircases for Congestion Reduction.
CoRR, 2018

2017
DISASTER: Dedicated Intelligent Security Attacks on Sensor-Triggered Emergency Responses.
IEEE Trans. Multi-Scale Computing Systems, 2017

Wearable Medical Sensor-Based System Design: A Survey.
IEEE Trans. Multi-Scale Computing Systems, 2017

CABA: Continuous Authentication Based on BioAura.
IEEE Trans. Computers, 2017

Multi-objective Optimization of Placement and Assignment of TSVs in 3D ICs.
Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017

A Method to Reduce Resources for Quantum Error Correction.
Proceedings of the Reversible Computation - 9th International Conference, 2017

Post-Layout Perturbation towards Stitch Friendly Layout for Multiple E-Beam Lithography.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

2016
Physiological Information Leakage: A New Frontier in Health Information Security.
IEEE Trans. Emerging Topics Comput., 2016

Embedding of signatures in reconfigurable scan architecture for authentication of intellectual properties in system-on-chip.
IET Computers & Digital Techniques, 2016

Error tracing in linear and concatenated quantum circuits.
CoRR, 2016

A Novel EPE Aware Hybrid Global Route Planner after Floorplanning.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

An early global routing framework for uniform wire distribution in SoCs.
Proceedings of the 29th IEEE International System-on-Chip Conference, 2016

An efficient synthesis method for ternary reversible logic.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015
Watermarking in Hard Intellectual Property for Pre-Fab and Post-Fab Verification.
IEEE Trans. VLSI Syst., 2015

PAQCS: Physical Design-Aware Fault-Tolerant Quantum Circuit Synthesis.
IEEE Trans. VLSI Syst., 2015

Energy-Efficient Long-term Continuous Personal Health Monitoring.
IEEE Trans. Multi-Scale Computing Systems, 2015

Systematic Poisoning Attacks on and Defenses for Machine Learning in Healthcare.
IEEE J. Biomedical and Health Informatics, 2015

Quantum Ternary Circuit Synthesis Using Projection Operations.
Multiple-Valued Logic and Soft Computing, 2015

Approximation algorithms for maximum independent set of a unit disk graph.
Inf. Process. Lett., 2015

Flare reduction in EUV Lithography by perturbation of wire segments.
Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015

A New Method for Defining Monotone Staircases in VLSI Floorplans.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

2014
A Modular Design to Synthesize Symmetric Functions Using Quantum Quaternary Logic.
J. Low Power Electronics, 2014

Global Routing Using Monotone Staircases with Minimal Bends.
Proceedings of the 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems, 2014

A novel architecture for QPSK modulation based on time-mode signal processing.
Proceedings of the 18th International Symposium on VLSI Design and Test, 2014

Synthesis of Ternary Grover's Algorithm.
Proceedings of the IEEE 44th International Symposium on Multiple-Valued Logic, 2014

Energy-Aware H.264 Decoding.
Proceedings of the Distributed Computing and Internet Technology, 2014

Trusted sharing of intellectual property in electronic hardware design.
Proceedings of the 9th Workshop on Embedded Systems Security, 2014

2013
A Cache-Aware Strategy for H.264 Decoding on Multi-processor Architectures.
Proceedings of the VLSI Design and Test, 17th International Symposium, 2013

STAIRoute: Global routing using monotone staircase channels.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013

Modular Design for Symmetric Functions Using Quantum Quaternary Logic.
Proceedings of the 2013 International Symposium on Electronic System Design, 2013

2012
Secure Public Verification of IP Marks in FPGA Design Through a Zero-Knowledge Protocol.
IEEE Trans. VLSI Syst., 2012

Tutorial T4: Intellectual Property Protection and Security in System-on-Chip Design.
Proceedings of the 25th International Conference on VLSI Design, 2012

A Synthesis Method for Quaternary Quantum Logic Circuits.
Proceedings of the Progress in VLSI Design and Test - 16th International Symposium, 2012

A Faster Hierarchical Balanced Bipartitioner for VLSI Floorplans Using Monotone Staircase Cuts.
Proceedings of the Progress in VLSI Design and Test - 16th International Symposium, 2012

Intellectual property protection and security of SoCs - An embedded tutorial.
Proceedings of the IEEE 25th International SOC Conference, 2012

2011
SoC: A Real Platform for IP Reuse, IP Infringement, and IP Protection.
VLSI Design, 2011

Floorplanning for Partially Reconfigurable FPGAs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2011

Cone-based placement for field programmable gate arrays.
IET Computers & Digital Techniques, 2011

Linear Nearest Neighbor Synthesis of Reversible Circuits by Graph Partitioning
CoRR, 2011

TSV-aware Scan Chain Reordering for 3D IC.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

Synthesis Techniques for Ternary Quantum Logic.
Proceedings of the 41st IEEE International Symposium on Multiple-Valued Logic, 2011

2010
Robust intellectual property protection of VLSI physical design.
IET Computers & Digital Techniques, 2010

Test pattern generation for droop faults.
IET Computers & Digital Techniques, 2010

A Unified Approach for IP Protection across Design Phases in a Packaged Chip.
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010

2009
FPGA placement using space-filling curves: Theory meets practice.
ACM Trans. Embedded Comput. Syst., 2009

Fast Unified Floorplan Topology Generation and Sizing on Heterogeneous FPGAs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2009

The Double Digest Problem: finding all solutions.
IJBRA, 2009

Droop sensitivity of stuck-at fault tests.
IET Computers & Digital Techniques, 2009

MAkE: Multiobjective algorithm for k-way equipartitioning of a point set.
Appl. Soft Comput., 2009

Encoding of Floorplans through Deterministic Perturbation.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

Floorplanning for Partial Reconfiguration in FPGAs.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

Secure Leakage-Proof Public Verification of IP Marks in VLSI Physical Design.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009

2008
Floorplanning.
Proceedings of the Handbook of Algorithms for Physical Design Automation., 2008

2007
Hierarchical partitioning of VLSI floorplans by staircases.
ACM Trans. Design Autom. Electr. Syst., 2007

Nearest Neighbour based Synthesis of Quantum Boolean Circuits.
Engineering Letters, 2007

Floorplanning in Modern FPGAs.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

A Novel Scheme for Encoding and Watermark Embedding in VLSI Physical Design for IP Protection.
Proceedings of the 2007 International Conference on Computing: Theory and Applications (ICCTA 2007), 2007

Faster Placer for Island-Style FPGAs.
Proceedings of the 2007 International Conference on Computing: Theory and Applications (ICCTA 2007), 2007

Fast Robust Intellectual Property Protection for VLSI Physical Design.
Proceedings of the 10th International Conference on Information Technology, 2007

2006
Test Pattern Generation for Power Supply Droop Faults.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

Multiobjective Genetic Algorithm for k-way Equipartitioning of a Point Set with Application to CAD-VLSI.
Proceedings of the 9th International Conference in Information Technology, 2006

2005
Hot Spots and Zones in a Chip: A Geometrician's View.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Genetic Algorithm for Double Digest Problem.
Proceedings of the Pattern Recognition and Machine Intelligence, 2005

Fast FPGA Placement using Space-filling Curve.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

2004
Manhattan-diagonal routing in channels and switchboxes.
ACM Trans. Design Autom. Electr. Syst., 2004

Physical Design Trends and Layout-Based Fault Modeling.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Virtual Molecular Computing - Emulating DNA Molecules.
Proceedings of the Distributed Computing, 2004

A Modeling Approach for Addressing Power Supply Switching Noise Related Failures of Integrated Circuit.
Proceedings of the 2004 Design, 2004

2003
Flavours of Traveling Salesman Problem in VLSI Design.
Proceedings of the 1st Indian International Conference on Artificial Intelligence, 2003

2001
Slicible rectangular graphs and their optimal floorplans.
ACM Trans. Design Autom. Electr. Syst., 2001

Partitioning Routing Area into Zones with Distinct Pins.
Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

Combined instruction and loop parallelism in array synthesis for FPGAs.
Proceedings of the 14th International Symposium on Systems Synthesis, 2001

Area(number)-balanced hierarchy of staircase channels with minimum crossing nets.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Combining Instruction and Loop Level Parallelism for FPGAs.
Proceedings of the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2001

2000
Topological Routing Amidst Polygonal Obstacles.
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

Optimal Partitioning for FPGA Based Regular Array Implementations.
Proceedings of the 2000 International Conference on Parallel Computing in Electrical Engineering (PARELEC 2000), 2000

Fsimac: a fault simulator for asynchronous sequential circuits.
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

1998
A unified approach to topology generation and optimal sizing of floorplans.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1998

Routing of L-Shaped Channels, Switchboxes and Staircases in Manhattan-Diagonal Model.
Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

1997
Slicibility of rectangular graphs and floorplan optimization.
Proceedings of the 1997 International Symposium on Physical Design, 1997

1995
VLSI floorplan generation and area optimization using AND-OR graph search.
Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995

A unified approach to topology generation and area optimization of general floorplans.
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

Efficient Algorithms for Vertex Arboricity of Planar Graphs.
Proceedings of the Foundations of Software Technology and Theoretical Computer Science, 1995

1992
Canonical Embedding of Rectangular Duals with Applications to VLSI Floorplanning.
Proceedings of the 29th Design Automation Conference, 1992

1991
The Cycle Structure of Channel Graphs in Nonslicible Floorplans and A Unified Algorithm for Feasible Routing Order.
Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991

1988
Inherent Nonslicibility of Rectangular Duals in VLSI Floorplanning.
Proceedings of the Foundations of Software Technology and Theoretical Computer Science, 1988


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