Susmita Sur-Kolay

Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

2023

Test Optimization in Memristor Crossbars Based on Path Selection.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023

Designing Ternary Quantum Error Correcting Codes from Binary Codes.

[BibT_eX]

[DOI]

J. Multiple Valued Log. Soft Comput., 2023

Concurrent Steiner Tree Selection for Global routing with EUVL Flare Reduction.

[BibT_eX]

[DOI]

Integr., 2023

FragQC: An Efficient Quantum Error Reduction Technique using Quantum Circuit Fragmentation.

[BibT_eX]

[DOI]

CoRR, 2023

AgEncID: Aggregate Encryption Individual Decryption of Key for FPGA Bitstream IP Cores in Cloud.

[BibT_eX]

[DOI]

CoRR, 2023

Fast 3D Volumetric Image Reconstruction from 2D MRI Slices by Parallel Processing.

[BibT_eX]

[DOI]

CoRR, 2023

2022

Faster search of clustered marked states with lackadaisical quantum walks.

[BibT_eX]

[DOI]

Quantum Inf. Process., 2022

Efficient Machine-Learning-based decoder for Heavy Hexagonal QECC.

[BibT_eX]

[DOI]

CoRR, 2022

Test Generation for SystemC designs by interlaced Greybox Fuzzing and Concolic Execution.

[BibT_eX]

[DOI]

Mukta Debnath

CoRR, 2022

Stitch-avoiding Global Routing for Multiple E-Beam Lithography.

[BibT_eX]

[DOI]

Proceedings of the 35th International Conference on VLSI Design and 2022 21st International Conference on Embedded Systems, 2022

Stitch-avoiding Detailed Routing for Multiple E-Beam Lithography.

[BibT_eX]

[DOI]

Kritanta Saha

Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022

Memristive Neural Network with Efficient In-Situ Supervised Training.

[BibT_eX]

[DOI]

Santlal Prajaprati

Proceedings of the 35th IEEE International System-on-Chip Conference, 2022

GreyConE: Greybox Fuzzing + Concolic Execution Guided Test Generation for High Level Designs.

[BibT_eX]

[DOI]

Mukta Debnath

Proceedings of the IEEE International Test Conference, 2022

2021

Minimization of WCRT with Recovery Assurance from Hardware Trojans for Tasks on FPGA-based Cloud.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2021

A study on flare minimisation in EUV lithography by post-layout re-allocation of wire segments.

[BibT_eX]

[DOI]

IET Circuits Devices Syst., 2021

FuCE: Fuzzing+Concolic Execution guided Trojan Detection in Synthesizable Hardware Designs.

[BibT_eX]

[DOI]

Mukta Debnath

CoRR, 2021

Depth Optimized Ansatz Circuit in QAOA for Max-Cut.

[BibT_eX]

[DOI]

CoRR, 2021

Optimizing Ansatz Design in QAOA for Max-cut.

[BibT_eX]

[DOI]

CoRR, 2021

3D Reconstruction from Micro-CT Slices for Non-Destructive Viewing inside a Fossil.

[BibT_eX]

[DOI]

Proceedings of the 36th International Conference on Image and Vision Computing New Zealand, 2021

2020

3D reconstruction of spine image from 2D MRI slices along one axis.

[BibT_eX]

[DOI]

IET Image Process., 2020

Asymptotically Improved Grover's Algorithm in any Dimensional Quantum System with Novel Decomposed n-qudit Toffoli Gate.

[BibT_eX]

[DOI]

CoRR, 2020

Exploiting degeneracy to construct good ternary quantum error correcting code.

[BibT_eX]

[DOI]

CoRR, 2020

Current Comparator-Based Reconfigurable Adder and Multiplier on Hybrid Memristive Crossbar.

[BibT_eX]

[DOI]

Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

Approximate Ternary Quantum Error Correcting Code with Low Circuit Cost.

[BibT_eX]

[DOI]

Proceedings of the 50th IEEE International Symposium on Multiple-Valued Logic, 2020

Special Session: Quantum Error Correction in Near Term Systems.

[BibT_eX]

[DOI]

Proceedings of the 38th IEEE International Conference on Computer Design, 2020

2019

Guided GA-Based Multiobjective Optimization of Placement and Assignment of TSVs in 3-D ICs.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2019

Selective Sensitization of Useless Sneak-Paths for Test Optimization in Memristor-Arrays.

[BibT_eX]

[DOI]

Manobennath Mondal

Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019

Minimization of Flare in EUVL by Simultaneous Wire Segment Perturbation and Dummification.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

Fault Coverage of a Test Set on Structure-Preserving Siblings of a Circuit-Under-Test.

[BibT_eX]

[DOI]

Manjari Pradhan

Proceedings of the 28th IEEE Asian Test Symposium, 2019

2018

Exploring the Scope of Unconstrained Via Minimization by Recursive Floorplan Bipartitioning.

[BibT_eX]

[DOI]

CoRR, 2018

Early Routability Assessment in VLSI Floorplans: A Generalized Routing Model.

[BibT_eX]

[DOI]

CoRR, 2018

STAIRoute: Early Global Routing using Monotone Staircases for Congestion Reduction.

[BibT_eX]

[DOI]

CoRR, 2018

2017

DISASTER: Dedicated Intelligent Security Attacks on Sensor-Triggered Emergency Responses.

[BibT_eX]

[DOI]

IEEE Trans. Multi Scale Comput. Syst., 2017

Wearable Medical Sensor-Based System Design: A Survey.

[BibT_eX]

[DOI]

IEEE Trans. Multi Scale Comput. Syst., 2017

CABA: Continuous Authentication Based on BioAura.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2017

Multi-objective Optimization of Placement and Assignment of TSVs in 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017

A Method to Reduce Resources for Quantum Error Correction.

[BibT_eX]

[DOI]

Saikat Basu

Proceedings of the Reversible Computation - 9th International Conference, 2017

Post-Layout Perturbation towards Stitch Friendly Layout for Multiple E-Beam Lithography.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

2016

Physiological Information Leakage: A New Frontier in Health Information Security.

[BibT_eX]

[DOI]

IEEE Trans. Emerg. Top. Comput., 2016

Embedding of signatures in reconfigurable scan architecture for authentication of intellectual properties in system-on-chip.

[BibT_eX]

[DOI]

IET Comput. Digit. Tech., 2016

Error tracing in linear and concatenated quantum circuits.

[BibT_eX]

[DOI]

Saikat Basu

Priyanka Mukhopadhyay

CoRR, 2016

A Novel EPE Aware Hybrid Global Route Planner after Floorplanning.

[BibT_eX]

[DOI]

Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

An early global routing framework for uniform wire distribution in SoCs.

[BibT_eX]

[DOI]

Proceedings of the 29th IEEE International System-on-Chip Conference, 2016

An efficient synthesis method for ternary reversible logic.

[BibT_eX]

[DOI]

Saikat Basu

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015

Watermarking in Hard Intellectual Property for Pre-Fab and Post-Fab Verification.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

PAQCS: Physical Design-Aware Fault-Tolerant Quantum Circuit Synthesis.

[BibT_eX]

[DOI]

Chia-Chun Lin

Niraj K. Jha

IEEE Trans. Very Large Scale Integr. Syst., 2015

Energy-Efficient Long-term Continuous Personal Health Monitoring.

[BibT_eX]

[DOI]

Arsalan Mohsen Nia

Mehran Mozaffari Kermani

Anand Raghunathan

Niraj K. Jha

IEEE Trans. Multi Scale Comput. Syst., 2015

Systematic Poisoning Attacks on and Defenses for Machine Learning in Healthcare.

[BibT_eX]

[DOI]

Mehran Mozaffari Kermani

Anand Raghunathan

Niraj K. Jha

IEEE J. Biomed. Health Informatics, 2015

Quantum Ternary Circuit Synthesis Using Projection Operations.

[BibT_eX]

[DOI]

J. Multiple Valued Log. Soft Comput., 2015

Approximation algorithms for maximum independent set of a unit disk graph.

[BibT_eX]

[DOI]

Inf. Process. Lett., 2015

Flare reduction in EUV Lithography by perturbation of wire segments.

[BibT_eX]

[DOI]

Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015

A New Method for Defining Monotone Staircases in VLSI Floorplans.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

2014

A Modular Design to Synthesize Symmetric Functions Using Quantum Quaternary Logic.

[BibT_eX]

[DOI]

Arighna Deb

Debesh Kumar Das

J. Low Power Electron., 2014

Global Routing Using Monotone Staircases with Minimal Bends.

[BibT_eX]

[DOI]

Proceedings of the 2014 27th International Conference on VLSI Design, 2014

A novel architecture for QPSK modulation based on time-mode signal processing.

[BibT_eX]

[DOI]

Sumit Saha

Proceedings of the 18th International Symposium on VLSI Design and Test, 2014

Synthesis of Ternary Grover's Algorithm.

[BibT_eX]

[DOI]

Proceedings of the IEEE 44th International Symposium on Multiple-Valued Logic, 2014

Energy-Aware H.264 Decoding.

[BibT_eX]

[DOI]

Arani Bhattacharya

Ansuman Banerjee

Proceedings of the Distributed Computing and Internet Technology, 2014

Trusted sharing of intellectual property in electronic hardware design.

[BibT_eX]

[DOI]

Proceedings of the 9th Workshop on Embedded Systems Security, 2014

2013

A Cache-Aware Strategy for H.264 Decoding on Multi-processor Architectures.

[BibT_eX]

[DOI]

Proceedings of the VLSI Design and Test, 17th International Symposium, 2013

STAIRoute: Global routing using monotone staircase channels.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013

Modular Design for Symmetric Functions Using Quantum Quaternary Logic.

[BibT_eX]

[DOI]

Arighna Deb

Debesh K. Das

Proceedings of the 2013 International Symposium on Electronic System Design, 2013

2012

Secure Public Verification of IP Marks in FPGA Design Through a Zero-Knowledge Protocol.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2012

Tutorial T4: Intellectual Property Protection and Security in System-on-Chip Design.

[BibT_eX]

[DOI]

Swarup Bhunia

Proceedings of the 25th International Conference on VLSI Design, 2012

A Synthesis Method for Quaternary Quantum Logic Circuits.

[BibT_eX]

[DOI]

Proceedings of the Progress in VLSI Design and Test - 16th International Symposium, 2012

A Faster Hierarchical Balanced Bipartitioner for VLSI Floorplans Using Monotone Staircase Cuts.

[BibT_eX]

[DOI]

Sridhar H. Rangarajan

Proceedings of the Progress in VLSI Design and Test - 16th International Symposium, 2012

Intellectual property protection and security of SoCs - An embedded tutorial.

[BibT_eX]

[DOI]

Proceedings of the IEEE 25th International SOC Conference, 2012

2011

SoC: A Real Platform for IP Reuse, IP Infringement, and IP Protection.

[BibT_eX]

[DOI]

VLSI Design, 2011

Floorplanning for Partially Reconfigurable FPGAs.

[BibT_eX]

[DOI]

Megha Sangtani

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Cone-based placement for field programmable gate arrays.

[BibT_eX]

[DOI]

IET Comput. Digit. Tech., 2011

Linear Nearest Neighbor Synthesis of Reversible Circuits by Graph Partitioning

[BibT_eX]

[DOI]

Ayan Chaudhury

CoRR, 2011

TSV-aware Scan Chain Reordering for 3D IC.

[BibT_eX]

[DOI]

Ayan Datta

Charudhattan Nagarajan

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

Synthesis Techniques for Ternary Quantum Logic.

[BibT_eX]

[DOI]

Proceedings of the 41st IEEE International Symposium on Multiple-Valued Logic, 2011

2010

Robust intellectual property protection of VLSI physical design.

[BibT_eX]

[DOI]

IET Comput. Digit. Tech., 2010

Test pattern generation for droop faults.

[BibT_eX]

[DOI]

Debasis Mitra

Sandip Kundu

Ashish Nigam

Sandeep K. Dey

IET Comput. Digit. Tech., 2010

A Unified Approach for IP Protection across Design Phases in a Packaged Chip.

[BibT_eX]

[DOI]

Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010

2009

FPGA placement using space-filling curves: Theory meets practice.

[BibT_eX]

[DOI]

Subhasis Bhattacharjee

ACM Trans. Embed. Comput. Syst., 2009

Fast Unified Floorplan Topology Generation and Sizing on Heterogeneous FPGAs.

[BibT_eX]

[DOI]

Arijit Bishnu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

The Double Digest Problem: finding all solutions.

[BibT_eX]

[DOI]

Satyajit Banerjee

Srabani Mukhopadhyaya

C. A. Murthy

Int. J. Bioinform. Res. Appl., 2009

Droop sensitivity of stuck-at fault tests.

[BibT_eX]

[DOI]

Debasis Mitra

IET Comput. Digit. Tech., 2009

MAkE: Multiobjective algorithm for k-way equipartitioning of a point set.

[BibT_eX]

[DOI]

Sriparna Saha

Sanghamitra Bandyopadhyay

Appl. Soft Comput., 2009

Encoding of Floorplans through Deterministic Perturbation.

[BibT_eX]

[DOI]

Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

Floorplanning for Partial Reconfiguration in FPGAs.

[BibT_eX]

[DOI]

Megha Sangtani

Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

Secure Leakage-Proof Public Verification of IP Marks in VLSI Physical Design.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009

2008

Floorplanning.

[BibT_eX]

[DOI]

Proceedings of the Handbook of Algorithms for Physical Design Automation., 2008

An Analytical Approach to Direct IP Protection of VLSI Floorplans.

[BibT_eX]

[DOI]

Proceedings of the IEEE Reglon 10 Colloquium and Third International Conference on Industrial and Information Systems, 2008

2007

Hierarchical partitioning of VLSI floorplans by staircases.

[BibT_eX]

[DOI]

Subhashis Majumder

Swarup Kumar Das

ACM Trans. Design Autom. Electr. Syst., 2007

Nearest Neighbour based Synthesis of Quantum Boolean Circuits.

[BibT_eX]

[DOI]

Eng. Lett., 2007

Floorplanning in Modern FPGAs.

[BibT_eX]

[DOI]

Arijit Bishnu

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

A Novel Scheme for Encoding and Watermark Embedding in VLSI Physical Design for IP Protection.

[BibT_eX]

[DOI]

Samar Sen-Sarma

Proceedings of the 2007 International Conference on Computing: Theory and Applications (ICCTA 2007), 2007

Faster Placer for Island-Style FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Conference on Computing: Theory and Applications (ICCTA 2007), 2007

Fast Robust Intellectual Property Protection for VLSI Physical Design.

[BibT_eX]

[DOI]

Proceedings of the 10th International Conference on Information Technology, 2007

2006

Test Pattern Generation for Power Supply Droop Faults.

[BibT_eX]

[DOI]

Debasis Mitra

Subhasis Bhattacharjee

Sujit T. Zachariah

Sandip Kundu

Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

Multiobjective Genetic Algorithm for k-way Equipartitioning of a Point Set with Application to CAD-VLSI.

[BibT_eX]

[DOI]

Sriparna Saha

Sanghamitra Bandyopadhyay

Proceedings of the 9th International Conference in Information Technology, 2006

2005

Hot Spots and Zones in a Chip: A Geometrician's View.

[BibT_eX]

[DOI]

Subhashis Majumder

Subhas C. Nandy

B. Chakraborty

Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Genetic Algorithm for Double Digest Problem.

[BibT_eX]

[DOI]

Satyajit Banerjee

Srabani Mukhopadhyaya

C. A. Murthy

Proceedings of the Pattern Recognition and Machine Intelligence, 2005

Fast FPGA Placement using Space-filling Curve.

[BibT_eX]

[DOI]

Subhasis Bhattacharjee

Sandip Das

Subhas C. Nandy

Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

2004

Manhattan-diagonal routing in channels and switchboxes.

[BibT_eX]

[DOI]

Sandip Das

ACM Trans. Design Autom. Electr. Syst., 2004

Physical Design Trends and Layout-Based Fault Modeling.

[BibT_eX]

[DOI]

Sujit T. Zachariah

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Virtual Molecular Computing - Emulating DNA Molecules.

[BibT_eX]

[DOI]

Sanjay Goswami

Proceedings of the Distributed Computing, 2004

A Modeling Approach for Addressing Power Supply Switching Noise Related Failures of Integrated Circuit.

[BibT_eX]

[DOI]

Proceedings of the 2004 Design, 2004

2003

Flavours of Traveling Salesman Problem in VLSI Design.

[BibT_eX]

Satyajit Banerjee

C. A. Murthy

Proceedings of the 1st Indian International Conference on Artificial Intelligence, 2003

2001

Slicible rectangular graphs and their optimal floorplans.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2001

Partitioning Routing Area into Zones with Distinct Pins.

[BibT_eX]

[DOI]

Koushik Sinha

P. S. Dasgupta

Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

Combined instruction and loop parallelism in array synthesis for FPGAs.

[BibT_eX]

[DOI]

Steven Derrien

Sanjay V. Rajopadhye

Proceedings of the 14th International Symposium on Systems Synthesis, 2001

Area(number)-balanced hierarchy of staircase channels with minimum crossing nets.

[BibT_eX]

[DOI]

Subhashis Majumder

Subhas C. Nandy

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Combining Instruction and Loop Level Parallelism for FPGAs.

[BibT_eX]

[DOI]

Steven Derrien

Sanjay V. Rajopadhye

Proceedings of the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2001

2000

Topological Routing Amidst Polygonal Obstacles.

[BibT_eX]

[DOI]

Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

Optimal Partitioning for FPGA Based Regular Array Implementations.

[BibT_eX]

[DOI]

Steven Derrien

Sanjay V. Rajopadhye

Proceedings of the 2000 International Conference on Parallel Computing in Electrical Engineering (PARELEC 2000), 2000

Fsimac: a fault simulator for asynchronous sequential circuits.

[BibT_eX]

[DOI]

Marly Roncken

Ken S. Stevens

Parimal Pal Chaudhuri

Rob Roy

Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

1998

A unified approach to topology generation and optimal sizing of floorplans.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

Routing of L-Shaped Channels, Switchboxes and Staircases in Manhattan-Diagonal Model.

[BibT_eX]

[DOI]

Sandip Das

Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

1997

Slicibility of rectangular graphs and floorplan optimization.

[BibT_eX]

[DOI]

Proceedings of the 1997 International Symposium on Physical Design, 1997

1995

VLSI floorplan generation and area optimization using AND-OR graph search.

[BibT_eX]

[DOI]

P. S. Dasgupta

Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995

A unified approach to topology generation and area optimization of general floorplans.

[BibT_eX]

[DOI]

Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

Efficient Algorithms for Vertex Arboricity of Planar Graphs.

[BibT_eX]

[DOI]

Abhik Roychoudhury

Proceedings of the Foundations of Software Technology and Theoretical Computer Science, 1995

1992

Canonical Embedding of Rectangular Duals with Applications to VLSI Floorplanning.

[BibT_eX]

[DOI]

Proceedings of the 29th Design Automation Conference, 1992

1991

The Cycle Structure of Channel Graphs in Nonslicible Floorplans and A Unified Algorithm for Feasible Routing Order.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991

1988

Inherent Nonslicibility of Rectangular Duals in VLSI Floorplanning.

[BibT_eX]

[DOI]