Mukta Debnath

Orcid: 0000-0001-5478-5163

According to our database1, Mukta Debnath authored at least 11 papers between 2020 and 2025.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2025
GreyConE+: Efficient Rare-Target Test Generation for FPGA HLS Designs.
ACM Trans. Reconfigurable Technol. Syst., December, 2025

AFarePart: Accuracy-aware Fault-resilient Partitioner for DNN Edge Accelerators.
CoRR, December, 2025

Efficient Task Graph Generation for DNN Inference on FPGA-based SoC Platforms.
Proceedings of the 38th IEEE International System-on-Chip Conference, 2025

2024
Scalable Test Generation to Trigger Rare Targets in High-Level Synthesizable IPs for Cloud FPGAs.
CoRR, 2024

Aggregate Encryption Individual Decryption for FPGA Bitstream Protection on Cloud.
Proceedings of the International Symposium on Secure and Private Execution Environment Design, 2024

2023
AgEncID: Aggregate Encryption Individual Decryption of Key for FPGA Bitstream IP Cores in Cloud.
CoRR, 2023

2022
Test Generation for SystemC designs by interlaced Greybox Fuzzing and Concolic Execution.
CoRR, 2022

GreyConE: Greybox Fuzzing + Concolic Execution Guided Test Generation for High Level Designs.
Proceedings of the IEEE International Test Conference, 2022

2021
Energy and Makespan Aware Scheduling of Deadline Sensitive Tasks in the Cloud Environment.
J. Grid Comput., 2021

FuCE: Fuzzing+Concolic Execution guided Trojan Detection in Synthesizable Hardware Designs.
CoRR, 2021

2020
Energy and quality of service-aware virtual machine consolidation in a cloud data center.
J. Supercomput., 2020


  Loading...