According to our database1, Deepak Kachave authored at least 7 papers between 2016 and 2018.
Legend:Book In proceedings Article PhD thesis Other
Spatial and Temporal Redundancy for Transient Fault-Tolerant Datapath.
IEEE Trans. Aerospace and Electronic Systems, 2018
Effect of NBTI stress on DSP cores used in CE devices: threat model and performance estimation.
IET Computers & Digital Techniques, 2018
Forensic engineering for resolving ownership problem of reusable IP core generated during high level synthesis.
Future Generation Comp. Syst., 2018
Shielding CE Hardware Against Reverse-Engineering Attacks Through Functional Locking [Hardware Matters].
IEEE Consumer Electronics Magazine, 2018
Low cost fault tolerance against kc-cycle and km-unit transient for loop based control data flow graphs during physically aware high level synthesis.
Microelectronics Reliability, 2017
Integrating physical level design and high level synthesis for simultaneous multi-cycle transient and multiple transient fault resiliency of application specific datapath processors.
Microelectronics Reliability, 2016
Generating Multi-cycle and Multiple Transient Fault Resilient Design During Physically Aware High Level Synthesis.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016