Deepak Kachave
Orcid: 0000-0003-3181-4835
According to our database1,
Deepak Kachave
authored at least 11 papers
between 2016 and 2019.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2019
Low Cost Functional Obfuscation of Reusable IP Ores Used in CE Hardware Through Robust Locking.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
2018
IEEE Trans. Aerosp. Electron. Syst., 2018
Effect of NBTI stress on DSP cores used in CE devices: threat model and performance estimation.
IET Comput. Digit. Tech., 2018
Forensic engineering for resolving ownership problem of reusable IP core generated during high level synthesis.
Future Gener. Comput. Syst., 2018
Shielding CE Hardware Against Reverse-Engineering Attacks Through Functional Locking [Hardware Matters].
IEEE Consumer Electron. Mag., 2018
Integrating Compiler Driven Transformation and Simulated Annealing Based Floorplan for Optimized Transient Fault Tolerant DSP Cores.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2018
2017
Low cost fault tolerance against k<sub>c</sub>-cycle and k<sub>m</sub>-unit transient for loop based control data flow graphs during physically aware high level synthesis.
Microelectron. Reliab., 2017
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2017
2016
Integrating physical level design and high level synthesis for simultaneous multi-cycle transient and multiple transient fault resiliency of application specific datapath processors.
Microelectron. Reliab., 2016
Generating Multi-cycle and Multiple Transient Fault Resilient Design During Physically Aware High Level Synthesis.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2016