Dipanjan Roy

Orcid: 0000-0002-1669-1083

According to our database1, Dipanjan Roy authored at least 39 papers between 2013 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
Editorial: Temporal structure of neural processes coupling sensory, motor and cognitive functions of the brain, volume II.
Frontiers Comput. Neurosci., February, 2023

Securing Hardware Accelerator Against Reverse Engineering Attack.
Proceedings of the IEEE International Conference on Consumer Electronics, 2023

2022
Whole-Brain Network Models: From Physics to Bedside.
Frontiers Comput. Neurosci., 2022

Characterizing the Dynamic Reorganization in Healthy Ageing and Classification of Brain Age.
Proceedings of the International Joint Conference on Neural Networks, 2022

Securing Hardware Accelerator during High-level Synthesis.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2022

2021
Organization of directed functional connectivity among nodes of ventral attention network reveals the common network mechanisms underlying saliency processing across distinct spatial and spatio-temporal scales.
NeuroImage, 2021

2020
Lifespan associated global patterns of coherent neural communication.
NeuroImage, 2020

Large-scale Functional Integration, Rather than Functional Dissociation along Dorsal and Ventral Streams, Underlies Visual Perception and Action.
J. Cogn. Neurosci., 2020

Editorial: Temporal Structure of Neural Processes Coupling Sensory, Motor and Cognitive Functions of the Brain.
Frontiers Comput. Neurosci., 2020

2019
Low Cost Functional Obfuscation of Reusable IP Ores Used in CE Hardware Through Robust Locking.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Resting state dynamics meets anatomical structure: Temporal multiple kernel learning (tMKL) model.
NeuroImage, 2019

Signature-Free Watermark for Protecting Digital Signal Processing Cores Used in CE Devices [Hardware Matters].
IEEE Consumer Electron. Mag., 2019

Multilevel Watermark for Protecting DSP Kernel in CE Systems [Hardware Matters].
IEEE Consumer Electron. Mag., 2019

Empirical Mode Decomposition Algorithms for Classification of Single-Channel EEG Manifesting McGurk Effect.
Proceedings of the Intelligent Human Computer Interaction - 11th International Conference, 2019

Low-Overhead Robust RTL Signature for DSP Core Protection: New Paradigm for Smart CE Design.
Proceedings of the IEEE International Conference on Consumer Electronics, 2019

Low Cost Dual-Phase Watermark for Protecting CE Devices in IoT Framework.
Proceedings of the Security and Fault Tolerance in Internet of Things, 2019

2018
Low-Cost Obfuscated JPEG CODEC IP Core for Secure CE Hardware.
IEEE Trans. Consumer Electron., 2018

Triple-Phase Watermarking for Reusable IP Core Protection During Architecture Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Intellectual Property-Based Lossless Image Compression for Camera Systems [Hardware Matters].
IEEE Consumer Electron. Mag., 2018

Optimizing DSP Cores Using Design Transformation [Hardware Matters].
IEEE Consumer Electron. Mag., 2018

Obfuscated JPEG Image Decompression IP Core for Protecting Against Reverse Engineering [Hardware Matter].
IEEE Consumer Electron. Mag., 2018

Age, Disease, and Their Interaction Effects on Intrinsic Connectivity of Children and Adolescents in Autism Spectrum Disorder Using Functional Connectomics.
Brain Connect., 2018

A Framework for Hardware Efficient Reusable IP Core for Grayscale Image CODEC.
IEEE Access, 2018

Reusable intellectual property core protection for both buyer and seller.
Proceedings of the IEEE International Conference on Consumer Electronics, 2018

Multi-phase watermark for IP core protection.
Proceedings of the IEEE International Conference on Consumer Electronics, 2018

2017
DSP design protection in CE through algorithmic transformation based structural obfuscation.
IEEE Trans. Consumer Electron., 2017

Low cost optimized Trojan secured schedule at behavioral level for single & Nested loop control data flow graphs (Invited Paper).
Integr., 2017

Low overhead symmetrical protection of reusable IP core using robust fingerprinting and watermarking during high level synthesis.
Future Gener. Comput. Syst., 2017

Antipiracy-Aware IP Chipset Design for CE Devices: A Robust Watermarking Approach [Hardware Matters].
IEEE Consumer Electron. Mag., 2017

Automated low cost scheduling driven watermarking methodology for modern CAD high-level synthesis tools.
Adv. Eng. Softw., 2017

Enhancing Saliency of a Target Object Through Color Modification of Every Object Using Genetic Algorithm.
Proceedings of the Soft Computing for Problem Solving, 2017

An EEG-Based Image Annotation System.
Proceedings of the Computer Vision, Pattern Recognition, Image Processing, and Graphics, 2017

Mathematical Validation of HWT Based Lossless Image Compression.
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2017

Metastability of cortical BOLD signals in maturation and senescence.
Proceedings of the 2017 International Joint Conference on Neural Networks, 2017

Enhancing Saliency of an Object Using Genetic Algorithm.
Proceedings of the 14th Conference on Computer and Robot Vision, 2017

2016
Does the regulation of local excitation-inhibition balance aid in recovery of functional connectivity? A computational account.
NeuroImage, 2016

2014
The role of alpha-rhythm states in perceptual learning: insights from experiments and computational models.
Frontiers Comput. Neurosci., 2014

Using the Virtual Brain to Reveal the Role of Oscillations and Plasticity in Shaping Brain's Dynamical Landscape.
Brain Connect., 2014

2013
Inferring network properties of cortical neurons with synaptic coupling and parameter dispersion.
Frontiers Comput. Neurosci., 2013


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