Dipanjan Roy

According to our database1, Dipanjan Roy authored at least 23 papers between 2013 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.



In proceedings 
PhD thesis 


On csauthors.net:


Resting state dynamics meets anatomical structure: Temporal multiple kernel learning (tMKL) model.
NeuroImage, 2019

Signature-Free Watermark for Protecting Digital Signal Processing Cores Used in CE Devices [Hardware Matters].
IEEE Consumer Electronics Magazine, 2019

Multilevel Watermark for Protecting DSP Kernel in CE Systems [Hardware Matters].
IEEE Consumer Electronics Magazine, 2019

Low-Cost Obfuscated JPEG CODEC IP Core for Secure CE Hardware.
IEEE Trans. Consumer Electronics, 2018

Triple-Phase Watermarking for Reusable IP Core Protection During Architecture Synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

Intellectual Property-Based Lossless Image Compression for Camera Systems [Hardware Matters].
IEEE Consumer Electronics Magazine, 2018

Optimizing DSP Cores Using Design Transformation [Hardware Matters].
IEEE Consumer Electronics Magazine, 2018

Obfuscated JPEG Image Decompression IP Core for Protecting Against Reverse Engineering [Hardware Matter].
IEEE Consumer Electronics Magazine, 2018

A Framework for Hardware Efficient Reusable IP Core for Grayscale Image CODEC.
IEEE Access, 2018

Reusable intellectual property core protection for both buyer and seller.
Proceedings of the IEEE International Conference on Consumer Electronics, 2018

Multi-phase watermark for IP core protection.
Proceedings of the IEEE International Conference on Consumer Electronics, 2018

DSP design protection in CE through algorithmic transformation based structural obfuscation.
IEEE Trans. Consumer Electronics, 2017

Low cost optimized Trojan secured schedule at behavioral level for single & Nested loop control data flow graphs (Invited Paper).
Integration, 2017

Low overhead symmetrical protection of reusable IP core using robust fingerprinting and watermarking during high level synthesis.
Future Generation Comp. Syst., 2017

Antipiracy-Aware IP Chipset Design for CE Devices: A Robust Watermarking Approach [Hardware Matters].
IEEE Consumer Electronics Magazine, 2017

Automated low cost scheduling driven watermarking methodology for modern CAD high-level synthesis tools.
Advances in Engineering Software, 2017

An EEG-Based Image Annotation System.
Proceedings of the Computer Vision, Pattern Recognition, Image Processing, and Graphics, 2017

Metastability of cortical BOLD signals in maturation and senescence.
Proceedings of the 2017 International Joint Conference on Neural Networks, 2017

Enhancing Saliency of an Object Using Genetic Algorithm.
Proceedings of the 14th Conference on Computer and Robot Vision, 2017

Does the regulation of local excitation-inhibition balance aid in recovery of functional connectivity? A computational account.
NeuroImage, 2016

The role of alpha-rhythm states in perceptual learning: insights from experiments and computational models.
Front. Comput. Neurosci., 2014

Using the Virtual Brain to Reveal the Role of Oscillations and Plasticity in Shaping Brain's Dynamical Landscape.
Brain Connectivity, 2014

Inferring network properties of cortical neurons with synaptic coupling and parameter dispersion.
Front. Comput. Neurosci., 2013