Derek Tam

According to our database1, Derek Tam authored at least 16 papers between 2011 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
Merging by Matching Models in Task Subspaces.
CoRR, 2023

Resolving Interference When Merging Models.
CoRR, 2023

TIES-Merging: Resolving Interference When Merging Models.
Proceedings of the Advances in Neural Information Processing Systems 36: Annual Conference on Neural Information Processing Systems 2023, 2023

Evaluating the Factual Consistency of Large Language Models Through News Summarization.
Proceedings of the Findings of the Association for Computational Linguistics: ACL 2023, 2023

2022
Evaluating the Factual Consistency of Large Language Models Through Summarization.
CoRR, 2022

Few-Shot Parameter-Efficient Fine-Tuning is Better and Cheaper than In-Context Learning.
Proceedings of the Advances in Neural Information Processing Systems 35: Annual Conference on Neural Information Processing Systems 2022, 2022

Isochrony-Aware Neural Machine Translation for Automatic Dubbing.
Proceedings of the Interspeech 2022, 2022

2021
Prosody-Aware Neural Machine Translation for Dubbing.
CoRR, 2021

An Empirical Survey of Data Augmentation for Limited Data Learning in NLP.
CoRR, 2021

Improving and Simplifying Pattern Exploiting Training.
Proceedings of the 2021 Conference on Empirical Methods in Natural Language Processing, 2021

2020
Predicting Institution Hierarchies with Set-based Models.
Proceedings of the Conference on Automated Knowledge Base Construction, 2020

2019
Optimal Transport-based Alignment of Learned Character Representations for String Similarity.
Proceedings of the 57th Conference of the Association for Computational Linguistics, 2019

2016
10.3 An analog front-end for 100BASE-T1 automotive Ethernet in 28nm CMOS.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2014
A Full-Duplex Line Driver for Gigabit Ethernet With Rail-to-Rail Class-AB Output Stage in 28 nm CMOS.
IEEE J. Solid State Circuits, 2014

8.6 A full-duplex line driver for Gigabit Ethernet with rail-to-rail class-AB output stage in 28nm CMOS.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2011
A 65nm CMOS self-terminated open-drain IDAC line driver suitable for fast Ethernet applications.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011


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