Derek Wright
According to our database1,
Derek Wright authored at least 11 papers
between 2003 and 2026.
Collaborative distances:
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Bibliography
2026
CoRR, February, 2026
2025
FPGA Implementation of SNN Based Multiple Input Multiple Output Neurons Using LIF Model.
Proceedings of the IEEE Canadian Conference on Electrical and Computer Engineering, 2025
2021
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
Proceedings of the 28th IEEE International Conference on Electronics, 2021
2019
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
2018
Sense amplifier offset characterisation and test implications for low-voltage SRAMs in 65 nm.
Proceedings of the 23rd IEEE European Test Symposium, 2018
2009
IEEE Trans. Circuits Syst. I Regul. Pap., 2009
2006
IEEE Trans. Very Large Scale Integr. Syst., 2006
Match Line Sense Amplifiers with Positive Feedback for Low-Power Content Addressable Memories.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006
2005
Co-Scheduling of Computation and Data on Computer Clusters.
Proceedings of the 17th International Conference on Scientific and Statistical Database Management, 2005
2003
Transistor-Level Fault Analysis and Test Algorithm Development for Ternary Dynamic Content Addressable Memorie.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003