Manoj Sachdev

According to our database1, Manoj Sachdev authored at least 130 papers between 1993 and 2019.

Collaborative distances:

Awards

IEEE Fellow

IEEE Fellow 2012, "For contributions to test methodology for very large scale integrated circuits".

Timeline

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2019
A Parametric DFT Scheme for STT-MRAMs.
IEEE Trans. VLSI Syst., 2019

Hybrid Latch-Type Offset Tolerant Sense Amplifier for Low-Voltage SRAMs.
IEEE Trans. on Circuits and Systems, 2019

2018
A 290-mV, 3.34-MHz, 6T SRAM With pMOS Access Transistors and Boosted Wordline in 65-nm CMOS Technology.
J. Solid-State Circuits, 2018

An ESD transient clamp with 494 pA leakage current in GP 65 nm CMOS technology.
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018

Sense amplifier offset characterisation and test implications for low-voltage SRAMs in 65 nm.
Proceedings of the 23rd IEEE European Test Symposium, 2018

2016
A Low-Leakage, Robust ESD Clamp with Thyristor Delay Element in 65 nm CMOS Technology.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Radiation hardened pulsed-latches in 65-nm CMOS.
Proceedings of the 2016 IEEE Canadian Conference on Electrical and Computer Engineering, 2016

2015
Adjacent-MBU-Tolerant SEC-DED-TAEC-yAED Codes for Embedded SRAMs.
IEEE Trans. on Circuits and Systems, 2015

A Linear Comparator-Based Fully Digital Delay Element.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

VLSI implementation of high-throughput, low-energy, configurable MIMO detector.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Voltage-Boosted Synchronizers.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

An FPGA Implementation of a Timing-Error Tolerant Discrete Cosine Transform (Abstract Only).
Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015

A low energy SRAM-based physically unclonable function primitive in 28 nm CMOS.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

2014
A 167-ps 2.34-mW Single-Cycle 64-Bit Binary Tree Comparator With Constant-Delay Logic in 65-nm CMOS.
IEEE Trans. on Circuits and Systems, 2014

A body-bias based current sense amplifier for high-speed low-power embedded SRAMs.
Proceedings of the 27th IEEE International System-on-Chip Conference, 2014

A hybrid ESD clamp with thyristor delay element and diodes for low-leakage applications.
Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014

Embedded tutorial: Test and manufacturability for silicon photonics and 3D integration.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

A 0.4 V 75 kbit SRAM macro in 28 nm CMOS featuring a 3-adjacent MBU correcting ECC.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

A low-leakage, hybrid ESD power supply clamp in 65nm CMOS technology.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2013
Constant Delay Logic Style.
IEEE Trans. VLSI Syst., 2013

Analysis and Design of On-Chip Decoupling Capacitors.
IEEE Trans. VLSI Syst., 2013

An Energy-Efficient Offset-Cancelling Sense Amplifier.
IEEE Trans. on Circuits and Systems, 2013

A novel voltage-programmed pixel circuit with VT-shift compensation for AMOLED displays.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2012
Performance, Metastability, and Soft-Error Robustness Trade-offs for Flip-Flops in 40 nm CMOS.
IEEE Trans. on Circuits and Systems, 2012

A Low-Power High-Performance Single-Cycle Tree-Based 64-Bit Binary Comparator.
IEEE Trans. on Circuits and Systems, 2012

A soft error robust 32kb SRAM macro featuring access transistor-less 8T cell in 65-nm.
Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012

Suppression of on-chip power supply noise generated by a 64-bit static logic ALU block.
Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012

A read-assist write-back voltage sense amplifier for low voltage-operated SRAMs.
Proceedings of the IEEE 25th International SOC Conference, 2012

Power delivery: Droop, jitter, test and debug story (Tutorial).
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

A 148ps 135mW 64-bit adder with Constant-Delay logic in 65nm CMOS.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

2011
A Compact Hybrid Current/Voltage Sense Amplifier With Offset Cancellation for High-Speed SRAMs.
IEEE Trans. VLSI Syst., 2011

Experimental Results for Slow-speed Timing Characterization of High-speed Pipelined Datapaths.
J. Electronic Testing, 2011

Digitally programmable SRAM timing for nano-scale technologies.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Design and analysis of metastable-hardened and soft-error tolerant high-performance, low-power flip-flops.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Design and analysis of metastable-hardened flip-flops in sub-threshold region.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

Performance, metastability and soft-error robustness tradeoffs for flip-flops in 40nm CMOS.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

Multiprocessor FPGA implementation of a 2D digital filter.
Proceedings of the 24th Canadian Conference on Electrical and Computer Engineering, 2011

Analysis of power supply noise mitigation circuits.
Proceedings of the 24th Canadian Conference on Electrical and Computer Engineering, 2011

2010
Comparative analysis and study of metastability on high-performance flip-flops.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

2009
Low-Leakage Storage Cells for Ternary Content Addressable Memories.
IEEE Trans. VLSI Syst., 2009

An Analytical Model for Soft Error Critical Charge of Nanometric SRAMs.
IEEE Trans. VLSI Syst., 2009

A Low-Power Ternary CAM With Positive-Feedback Match-Line Sense Amplifiers.
IEEE Trans. on Circuits and Systems, 2009

An Energy Efficient 40 Kb SRAM Module With Extended Read/Write Noise Margin in 0.13 µm CMOS.
J. Solid-State Circuits, 2009

SRAM Cell Stability: A Dynamic Perspective.
J. Solid-State Circuits, 2009

Design and Analysis of A 5.3-pJ 64-kb Gated Ground SRAM With Multiword ECC.
J. Solid-State Circuits, 2009

Design of a 64-bit Low-energy High-performance Adder using Dynamic Feedthrough Logic.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

ESD protection circuit for 8.5Gbps I/Os in 90nm CMOS technology.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

ESD design challenges.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

2008
A 5-Gb/s CDR Circuit With Automatically Calibrated Linear Phase Detector.
IEEE Trans. on Circuits and Systems, 2008

Investigation of Process Impact on Soft Error Susceptibility of Nanometric SRAMs Using a Compact Critical Charge Model.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

A fully digital ADC using a new delay element with enhanced linearity.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

2007
Segmented Virtual Ground Architecture for Low-Power Embedded SRAM.
IEEE Trans. VLSI Syst., 2007

Variation-Aware Adaptive Voltage Scaling System.
IEEE Trans. VLSI Syst., 2007

Low-Capacitance and Charge-Shared Match Lines for Low-Energy High-Performance TCAMs.
J. Solid-State Circuits, 2007

Comparative Robustness of CML Phase Detectors for Clock and Data Recovery Circuits.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

A Novel Tri-State Binary Phase Detector.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Dynamic Data Stability in Low-power SRAM Design.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

Optimizing Circuit Performance and ESD Protection for High-Speed Differential I/Os.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006
Thermal and Power Management of Integrated Circuits
Series on Integrated Circuits and Systems, Springer, ISBN: 978-0-387-29749-1, 2006

Design techniques and test methodology for low-power TCAMs.
IEEE Trans. VLSI Syst., 2006

DTMOS Technique for Low-Voltage Analog Circuits.
IEEE Trans. VLSI Syst., 2006

Novel gate and substrate triggering techniques for deep sub-micron ESD protection devices.
Microelectronics Journal, 2006

New JETTA Editors, 2006.
J. Electronic Testing, 2006

Novel Ternary Storage Cells and Techniques for Leakage Reduction in Ternary CAM.
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

Low-Power Priority Encoder and Multiple Match Detection Circuit for Ternary Content Addressable Memory.
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

Dynamic Data Stability in SRAM Cells and Its Implications on Data Stability Tests.
Proceedings of the 14th IEEE International Workshop on Memory Technology, 2006

A low power SRAM architecture based on segmented virtual grounding.
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006

A phase-domain 2nd-order continuous time Delta-Sigma-modulator for frequency digitization.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A Phase-Domain Continuous-Time 2nd-Order ΔΣ Frequency Digitizer.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

Match Line Sense Amplifiers with Positive Feedback for Low-Power Content Addressable Memories.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

2005
Design of a 1.7-GHz low-power delay-fault-testable 32-b ALU in 180-nm CMOS technology.
IEEE Trans. VLSI Syst., 2005

Designing leakage tolerant, low power wide-OR dominos for sub-130nm CMOS technologies.
Microelectronics Journal, 2005

Word line pulsing technique for stability fault detection in SRAM cells.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Analysis and Design of LVTSCR-based EOS/ESD Protection Circuits for Burn-in Environment.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

A 0.8V Delta-Sigma modulator using DTMOS technique.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Programmable techniques for cell stability test and debug in embedded SRAMs.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2004
Correction to "A Digitally Programmable Delay Element: Design and Analysis".
IEEE Trans. VLSI Syst., 2004

A low-power reduced swing global clocking methodology.
IEEE Trans. VLSI Syst., 2004

The Impact of CMOS technology scaling on MOSFETs second breakdown: Evaluation of ESD robustness.
Microelectronics Reliability, 2004

Evaluation of STI degradation using temperature dependence of leakage current in parasitic STI MOSFET.
Microelectronics Reliability, 2004

DFT for Delay Fault Testing of High-Performance Digital Circuits.
IEEE Design & Test of Computers, 2004

AN SRAM Weak Cell Fault Model and a DFT Technique with a Programmable Detection Threshold.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

A DFT Technique for Delay Fault Testability and Diagnostics in 32-Bit High Performance CMOS ALUs.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Leakage Control Techniques for Designing Robust, Low Power Wide-OR Domino Logic for sub-130 nm CMOS Technologies.
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004

An Overview of Substrate Noise Reduction Techniques.
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004

Efficient adaptive voltage scaling system through on-chip critical path emulation.
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004

A CPL-based dual supply 32-bit ALU for sub 180nm CMOS technologies.
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004

Low power dual matchline ternary content addressable memory.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Modeling and designing energy-delay optimized wide domino circuits.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Design optimizations for microprocessors at low temperature.
Proceedings of the 41th Design Automation Conference, 2004

2003
A digitally programmable delay element: design and analysis.
IEEE Trans. VLSI Syst., 2003

Testing high-performance pipelined circuits with slow-speed testers.
ACM Trans. Design Autom. Electr. Syst., 2003

Leakage Current in Sub-Quarter Micron MOSFET: A Perspective on Stressed Delta IDDQ Testing.
J. Electronic Testing, 2003

A DFT Technique for Testing High-Speed Circuits with Arbitrarily Slow Testers.
J. Electronic Testing, 2003

Transistor-Level Fault Analysis and Test Algorithm Development for Ternary Dynamic Content Addressable Memorie.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Burn-in Temperature Projections for Deep Sub-micron Technologies.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Effectiveness and scaling trends of leakage control techniques for sub-130nm CMOS technologies.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

Thermal Management of High Performance Microprocessors.
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

DFT for Testing igh-Performance Pipelined Circuits with Slow-Speed Testers.
Proceedings of the 2003 Design, 2003

2002
A comparative analysis of low-power low-voltage dual-edge-triggered flip-flops.
IEEE Trans. VLSI Syst., 2002

Leakage and Process Variation Effects in Current Testing on Future CMOS Circuits.
IEEE Design & Test of Computers, 2002

Trends and Challenges in VLSI Technology Scaling towards 100nm (Tutorial Abstract).
Proceedings of the ASPDAC 2002 / VLSI Design 2002, 2002

Multi-Gigahertz Digital Test Challenges and Techniques.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

A DFT Technique for Low Frequency Delay Fault Testing in High Performance Digital Circuits.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Effect of Static Power Dissipation in Burn-In Environment on Yield of VLSI.
Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002

2001
Design for Delay Testability in High-Speed Digital ICs.
J. Electronic Testing, 2001

Current-Based Testing for Deep-Submicron VLSIs.
IEEE Design & Test of Computers, 2001

A Methodology for Testing High-Performance Circuits at Arbitrarily Low Test Frequency.
Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

Comparative delay and energy of single edge-triggered & dual edge-triggered pulsed flip-flops for high-performance microprocessors.
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

2000
A Low-Speed BIST Framework for High-Performance Circuit Testing.
Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

Multiple-parameter CMOS IC testing with increased sensitivity for I_DDQ.
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

1999
Off-Chip Diagnosis of Aperture Jitter in Full-Flash Analog-to-Digital Converters.
J. Electronic Testing, 1999

Configurations for IDDQ-Testable PLAs.
IEEE Design & Test of Computers, 1999

A DFT technique for high performance circuit testing.
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

1998
Defect detection with transient current testing and its potential for deep sub-micron CMOS ICs.
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

1997
Open Defects in CMOS RAM Address Decoders.
IEEE Design & Test of Computers, 1997

Deep sub-micron IDDQ testing: issues and solutions.
Proceedings of the European Design and Test Conference, 1997

1996
SeparateIDDQ testing of signal and bias paths in CMOS ICs for defect diagnosis.
J. Electronic Testing, 1996

Deep Sub-micron IDDQ Test Options.
Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

Low power, testable dual edge triggered flip-flops.
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996

Test and Testability Techniques for Open Defects in RAM Address Decoders.
Proceedings of the 1996 European Design and Test Conference, 1996

1995
A realistic defect oriented testability methodology for analog circuits.
J. Electronic Testing, 1995

Reducing the CMOS RAM test complexity withIDDQ and voltage testing.
J. Electronic Testing, 1995

Testing Defects in Scan Chains.
IEEE Design & Test of Computers, 1995

Industrial Relevance of Analog IFA: A Fact or a Fiction.
Proceedings of the Proceedings IEEE International Test Conference 1995, 1995

IDDQ and Voltage Testable CMOS Flip-flop Configurations.
Proceedings of the Proceedings IEEE International Test Conference 1995, 1995

Defect-oriented test methodology for complex mixed-signal circuits.
Proceedings of the 1995 European Design and Test Conference, 1995

1994
Transforming Sequential Logic in Digital CMOS ICs for Voltage and IDDQ Testing.
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

1993
Development of Fault Model and Test Algorithms for Embedded DRAMs.
Proceedings of the Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics, 1993

Catastrophic Defects Oriented Testability Analysis of a Class AB Amplifier.
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1993


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