Manoj Sachdev

According to our database, Manoj Sachdev authored at least 156 papers between 1993 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2023

Enhancing Strong PUF Security With Nonmonotonic Response Quantization.

Kleber Stangherlin, Zhuanhao Wu, Hiren D. Patel, Manoj Sachdev

IEEE Trans. Very Large Scale Integr. Syst., 2023

VLFF - A Very Low-power Flip-flop with only Two Clock Transistors.

Yugal Maheshwari, Manoj Sachdev

Proceedings of the 36th IEEE International System-on-Chip Conference, 2023

2022

Testchip Measured CRPs of NMQ strong PUF.

Kleber Stangherlin, Zhuanhao Wu, Hiren D. Patel, Manoj Sachdev

Dataset, June, 2022

Design and Implementation of a Secure RISC-V Microprocessor.

Kleber Stangherlin, Manoj Sachdev

IEEE Trans. Very Large Scale Integr. Syst., 2022

Secure and Lightweight Strong PUF Challenge Obfuscation with Keyed Non-linear FSR.

Kleber Stangherlin, Zhuanhao Wu, Hiren D. Patel, Manoj Sachdev

CoRR, 2022

Design Exploration and Security Assessment of PUF-on-PUF Implementations.

Kleber Stangherlin, Zhuanhao Wu, Hiren D. Patel, Manoj Sachdev

CoRR, 2022

Enhancing Strong PUF Security with Non-monotonic Response Quantization.

Kleber Stangherlin, Zhuanhao Wu, Hiren D. Patel, Manoj Sachdev

CoRR, 2022

2021

Body Biased Sense Amplifier With Auto-Offset Mitigation for Low-Voltage SRAMs.

Dhruv Patel, Adam Neale, Derek Wright, Manoj Sachdev

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Energy-Efficient Full-Swing Logic Circuits With Unipolar TFTs on Flexible Substrates.

Qing Li, Czang-Ho Lee, Mohsen Asad, William S. Wong, Manoj Sachdev

IEEE J. Solid State Circuits, 2021

Reliable Strong PUF Enrollment and Operation with Temperature and Voltage Optimization.

Kleber Hugo Stangherlin, Manoj Sachdev

Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021

Ultra Low-power, Low-energy Static Single-phase Clocked Flip-flop.

Yugal Maheshwari, Kleber Stangherlin, Derek Wright, Manoj Sachdev

Proceedings of the 28th IEEE International Conference on Electronics, 2021

2020

Monitoring Aging Defects in STT-MRAMs.

Govind Radhakrishnan, Youngki Yoon, Manoj Sachdev

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

A low-power low-offset charge-sharing technique for double-tail comparators.

Ata Khorami, Roghayeh Saeidi, Manoj Sachdev

Microelectron. J., 2020

Accelerating STT-MRAM Ramp-up Characterization.

Govind Radhakrishnan, Youngki Yoon, Manoj Sachdev

Proceedings of the 18th IEEE International New Circuits and Systems Conference, 2020

Realization of an Energy-Efficient, Full-Swing Decoder with Unipolar TFT Technology.

Qing Li, Czang-Ho Lee, William S. Wong, Manoj Sachdev

Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020

2019

A Parametric DFT Scheme for STT-MRAMs.

Govind Radhakrishnan, Youngki Yoon, Manoj Sachdev

IEEE Trans. Very Large Scale Integr. Syst., 2019

Hybrid Latch-Type Offset Tolerant Sense Amplifier for Low-Voltage SRAMs.

Dhruv Patel, Adam Neale, Derek Wright, Manoj Sachdev

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

A low-power dynamic comparator for low-offset applications.

Ata Khorami, Roghayeh Saeidi, Manoj Sachdev, Mohammad Sharifkhani

Integr., 2019

Tutorial 2B: Offset Mitigation in Low-Voltage Sense Amplifiers and Its Implication on SRAM Design and Test.

Manoj Sachdev

Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019

A Contention-free, Static, Single-phase Flip-Flop for Low Data Activity Applications.

Ata Khorami, Manoj Sachdev, Mohammad Sharifkhani

Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019

Strengthening PUFs using Composition.

Zhuanhao Wu, Hiren D. Patel, Manoj Sachdev, Mahesh V. Tripunitara

Proceedings of the International Conference on Computer-Aided Design, 2019

2018

A 290-mV, 3.34-MHz, 6T SRAM With pMOS Access Transistors and Boosted Wordline in 65-nm CMOS Technology.

Morteza Nabavi, Manoj Sachdev

IEEE J. Solid State Circuits, 2018

An ESD transient clamp with 494 pA leakage current in GP 65 nm CMOS technology.

Mahdi Elghazali, Manoj Sachdev, Ajoy Opal

Proceedings of the 19th International Symposium on Quality Electronic Design, 2018

Sense amplifier offset characterisation and test implications for low-voltage SRAMs in 65 nm.

Dhruv Patel, Derek Wright, Manoj Sachdev

Proceedings of the 23rd IEEE European Test Symposium, 2018

2016

A Low-Leakage, Robust ESD Clamp with Thyristor Delay Element in 65 nm CMOS Technology.

Mahdi Elghazali, Manoj Sachdev, Ajoy Opal

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Radiation hardened pulsed-latches in 65-nm CMOS.

Jaspal Singh Shah, Manoj Sachdev

Proceedings of the 2016 IEEE Canadian Conference on Electrical and Computer Engineering, 2016

2015

Adjacent-MBU-Tolerant SEC-DED-TAEC-yAED Codes for Embedded SRAMs.

Adam Neale, Maarten Jonkman, Manoj Sachdev

IEEE Trans. Circuits Syst. II Express Briefs, 2015

Runtime slack-deficit detection for a low-voltage DCT circuit.

Yaoqiang Li, Pierce I-Jen Chuang, Andrew A. Kennings, Manoj Sachdev

Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

A Linear Comparator-Based Fully Digital Delay Element.

Afshin Seraj, Mohammad Maymandi-Nejad, Parvin Bahmanyar, Manoj Sachdev

Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

VLSI implementation of high-throughput, low-energy, configurable MIMO detector.

Pierce I-Jen Chuang, Manoj Sachdev, Vincent C. Gaudet

Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Voltage-Boosted Synchronizers.

Yaoqiang Li, Pierce I-Jen Chuang, Andrew A. Kennings, Manoj Sachdev

Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

An FPGA Implementation of a Timing-Error Tolerant Discrete Cosine Transform (Abstract Only).

Yaoqiang Li, Pierce I-Jen Chuang, Andrew A. Kennings, Manoj Sachdev

Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015

A low energy SRAM-based physically unclonable function primitive in 28 nm CMOS.

Adam Neale, Manoj Sachdev

Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

2014

A 167-ps 2.34-mW Single-Cycle 64-Bit Binary Tree Comparator With Constant-Delay Logic in 65-nm CMOS.

Pierce I-Jen Chuang, Manoj Sachdev, Vincent C. Gaudet

IEEE Trans. Circuits Syst. I Regul. Pap., 2014

A body-bias based current sense amplifier for high-speed low-power embedded SRAMs.

Tahseen Shakir, Manoj Sachdev

Proceedings of the 27th IEEE International System-on-Chip Conference, 2014

A hybrid ESD clamp with thyristor delay element and diodes for low-leakage applications.

Mahdi Elghazali, Manoj Sachdev, Ajoy Opal

Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014

Embedded tutorial: Test and manufacturability for silicon photonics and 3D integration.

Manoj Sachdev, Tetsuya Iizuka

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

A 0.4 V 75 kbit SRAM macro in 28 nm CMOS featuring a 3-adjacent MBU correcting ECC.

Adam Neale, Manoj Sachdev

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

A low-leakage, hybrid ESD power supply clamp in 65nm CMOS technology.

Mahdi Elghazali, Manoj Sachdev, Ajoy Opal

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2013

Constant Delay Logic Style.

Pierce Chuang, David Li, Manoj Sachdev

IEEE Trans. Very Large Scale Integr. Syst., 2013

Analysis and Design of On-Chip Decoupling Capacitors.

Tasreen Charania, Ajoy Opal, Manoj Sachdev

IEEE Trans. Very Large Scale Integr. Syst., 2013

An Energy-Efficient Offset-Cancelling Sense Amplifier.

Jaspal Singh Shah, David Nairn, Manoj Sachdev

IEEE Trans. Circuits Syst. II Express Briefs, 2013

A novel voltage-programmed pixel circuit with VT-shift compensation for AMOLED displays.

Maofeng Yang, Nikolas P. Papadopoulos, Czang-Ho Lee, William S. Wong, Manoj Sachdev

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2012

Performance, Metastability, and Soft-Error Robustness Trade-offs for Flip-Flops in 40 nm CMOS.

David Rennie, David Li, Manoj Sachdev, Bharat L. Bhuva, Srikanth Jagannathan, Shi-Jie Wen, Richard Wong

IEEE Trans. Circuits Syst. I Regul. Pap., 2012

A Low-Power High-Performance Single-Cycle Tree-Based 64-Bit Binary Comparator.

Pierce Chuang, David Li, Manoj Sachdev

IEEE Trans. Circuits Syst. II Express Briefs, 2012

A soft error robust 32kb SRAM macro featuring access transistor-less 8T cell in 65-nm.

Jaspal Singh Shah, David Nairn, Manoj Sachdev

Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012

Suppression of on-chip power supply noise generated by a 64-bit static logic ALU block.

Tasreen Charania, Pierce Chuang, Ajoy Opal, Manoj Sachdev

Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012

A read-assist write-back voltage sense amplifier for low voltage-operated SRAMs.

Tahseen Shakir, Manoj Sachdev

Proceedings of the IEEE 25th International SOC Conference, 2012

A word-line boost driver design for low operating voltage 6T-SRAMs.

Tahseen Shakir, Manoj Sachdev

Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

Power delivery: Droop, jitter, test and debug story (Tutorial).

Mike Li, Manoj Sachdev

Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

A 148ps 135mW 64-bit adder with Constant-Delay logic in 65nm CMOS.

Pierce Chuang, David Li, Manoj Sachdev, Vincent C. Gaudet

Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

2011

A Compact Hybrid Current/Voltage Sense Amplifier With Offset Cancellation for High-Speed SRAMs.

Mohammad Sharifkhani, Ehsan Rahiminejad, Shah M. Jahinuzzaman, Manoj Sachdev

IEEE Trans. Very Large Scale Integr. Syst., 2011

Experimental Results for Slow-speed Timing Characterization of High-speed Pipelined Datapaths.

Muhammad Nummer, Manoj Sachdev

J. Electron. Test., 2011

Digitally programmable SRAM timing for nano-scale technologies.

Adam Neale, Manoj Sachdev

Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Design and analysis of metastable-hardened and soft-error tolerant high-performance, low-power flip-flops.

David Li, David Rennie, Pierce Chuang, David Nairn, Manoj Sachdev

Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Design and analysis of metastable-hardened flip-flops in sub-threshold region.

David Li, Pierce Chuang, David Nairn, Manoj Sachdev

Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

Performance, metastability and soft-error robustness tradeoffs for flip-flops in 40nm CMOS.

David Rennie, David Li, Manoj Sachdev, Bharat L. Bhuva, Srikanth Jagannathan, Shi-Jie Wen, Rick Wong

Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

Multiprocessor FPGA implementation of a 2D digital filter.

Danny Teng-Hsiang Tsuei, Mohamed-Yahia Dabbagh, Manoj Sachdev

Proceedings of the 24th Canadian Conference on Electrical and Computer Engineering, 2011

Analysis of power supply noise mitigation circuits.

Tasreen Charania, Pierce Chuang, Ajoy Opal, Manoj Sachdev

Proceedings of the 24th Canadian Conference on Electrical and Computer Engineering, 2011

2010

Comparative analysis and study of metastability on high-performance flip-flops.

David Li, Pierce Chuang, Manoj Sachdev

Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

2009

Low-Leakage Storage Cells for Ternary Content Addressable Memories.

Nitin Mohan, Manoj Sachdev

IEEE Trans. Very Large Scale Integr. Syst., 2009

An Analytical Model for Soft Error Critical Charge of Nanometric SRAMs.

Shah M. Jahinuzzaman, Mohammad Sharifkhani, Manoj Sachdev

IEEE Trans. Very Large Scale Integr. Syst., 2009

A Low-Power Ternary CAM With Positive-Feedback Match-Line Sense Amplifiers.

Nitin Mohan, Wilson Fung, Derek Wright, Manoj Sachdev

IEEE Trans. Circuits Syst. I Regul. Pap., 2009

An Energy Efficient 40 Kb SRAM Module With Extended Read/Write Noise Margin in 0.13 µm CMOS.

Mohammad Sharifkhani, Manoj Sachdev

IEEE J. Solid State Circuits, 2009

SRAM Cell Stability: A Dynamic Perspective.

Mohammad Sharifkhani, Manoj Sachdev

IEEE J. Solid State Circuits, 2009

Design and Analysis of A 5.3-pJ 64-kb Gated Ground SRAM With Multiword ECC.

Shah M. Jahinuzzaman, Jaspal Singh Shah, David J. Rennie, Manoj Sachdev

IEEE J. Solid State Circuits, 2009

Design of a 64-bit Low-energy High-performance Adder using Dynamic Feedthrough Logic.

Pierce Chuang, David Li, Manoj Sachdev

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

ESD protection circuit for 8.5Gbps I/Os in 90nm CMOS technology.

Hossein Sarbishaei, Manoj Sachdev

Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

ESD design challenges.

Manoj Sachdev, Hong-Ha Vuong

Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

2008

A 5-Gb/s CDR Circuit With Automatically Calibrated Linear Phase Detector.

David Rennie, Manoj Sachdev

IEEE Trans. Circuits Syst. I Regul. Pap., 2008

Investigation of Process Impact on Soft Error Susceptibility of Nanometric SRAMs Using a Compact Critical Charge Model.

Shah M. Jahinuzzaman, Mohammad Sharifkhani, Manoj Sachdev

Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

A fully digital ADC using a new delay element with enhanced linearity.

Hooman Farkhani, Mohammad Maymandi-Nejad, Manoj Sachdev

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

A multiword based high speed ECC scheme for low-voltage embedded SRAMS.

Shah M. Jahinuzzaman, Tahseen Shakir, Sumanjit Lubana, Jaspal Singh Shah, Manoj Sachdev

Proceedings of the ESSCIRC 2008, 2008

2007

Segmented Virtual Ground Architecture for Low-Power Embedded SRAM.

Mohammad Sharifkhani, Manoj Sachdev

IEEE Trans. Very Large Scale Integr. Syst., 2007

Variation-Aware Adaptive Voltage Scaling System.

Mohamed Elgebaly, Manoj Sachdev

IEEE Trans. Very Large Scale Integr. Syst., 2007

Low-Capacitance and Charge-Shared Match Lines for Low-Energy High-Performance TCAMs.

Nitin Mohan, Manoj Sachdev

IEEE J. Solid State Circuits, 2007

Comparative Robustness of CML Phase Detectors for Clock and Data Recovery Circuits.

David Rennie, Manoj Sachdev

Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

A Novel Tri-State Binary Phase Detector.

David Rennie, Manoj Sachdev

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Dynamic Data Stability in Low-power SRAM Design.

Mohammad Sharifkhani, Shah M. Jahinuzzaman, Manoj Sachdev

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

Optimizing Circuit Performance and ESD Protection for High-Speed Differential I/Os.

Hossein Sarbishaei, Oleg Semenov, Manoj Sachdev

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006

Thermal and Power Management of Integrated Circuits

Arman Vassighi, Manoj Sachdev

Series on Integrated Circuits and Systems, Springer, ISBN: 978-0-387-29749-1, 2006

Design techniques and test methodology for low-power TCAMs.

Nitin Mohan, Wilson Fung, Derek Wright, Manoj Sachdev

IEEE Trans. Very Large Scale Integr. Syst., 2006

DTMOS Technique for Low-Voltage Analog Circuits.

Mohammad Maymandi-Nejad, Manoj Sachdev

IEEE Trans. Very Large Scale Integr. Syst., 2006

Novel gate and substrate triggering techniques for deep sub-micron ESD protection devices.

Oleg Semenov, Hossein Sarbishaei, Valery Axelrad, Manoj Sachdev

Microelectron. J., 2006

Weak Cell Detection in Deep-Submicron SRAMs: A Programmable Detection Technique.

Andrei Pavlov, Manoj Sachdev, José Pineda de Gyvez

IEEE J. Solid State Circuits, 2006

New JETTA Editors, 2006.

Bashir M. Al-Hashimi, Dimitris Gizopoulos, Manoj Sachdev, Adit D. Singh

J. Electron. Test., 2006

Novel Ternary Storage Cells and Techniques for Leakage Reduction in Ternary CAM.

Nitin Mohan, Manoj Sachdev

Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

Low-Power Priority Encoder and Multiple Match Detection Circuit for Ternary Content Addressable Memory.

Nitin Mohan, Wilson Fung, Manoj Sachdev

Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

Dynamic Data Stability in SRAM Cells and Its Implications on Data Stability Tests.

Mohammad Sharifkhani, Shah M. Jahinuzzaman, Manoj Sachdev

Proceedings of the 14th IEEE International Workshop on Memory Technology, 2006

A low power SRAM architecture based on segmented virtual grounding.

Mohammad Sharifkhani, Manoj Sachdev

Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006

A phase-domain 2nd-order continuous time Delta-Sigma-modulator for frequency digitization.

Mohammad Sharifkhani, Manoj Sachdev

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A Phase-Domain Continuous-Time 2^nd-Order ΔΣ Frequency Digitizer.

Mohammad Sharifkhani, Manoj Sachdev

Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

Match Line Sense Amplifiers with Positive Feedback for Low-Power Content Addressable Memories.

Nitin Mohan, Wilson Fung, Derek Wright, Manoj Sachdev

Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

2005

Design of a 1.7-GHz low-power delay-fault-testable 32-b ALU in 180-nm CMOS technology.

Bhaskar Chatterjee, Manoj Sachdev

IEEE Trans. Very Large Scale Integr. Syst., 2005

Designing leakage tolerant, low power wide-OR dominos for sub-130nm CMOS technologies.

Bhaskar Chatterjee, Manoj Sachdev, Ram Krishnamurthy

Microelectron. J., 2005

A monotonic digitally controlled delay element.

Mohammad Maymandi-Nejad, Manoj Sachdev

IEEE J. Solid State Circuits, 2005

Word line pulsing technique for stability fault detection in SRAM cells.

Andrei Pavlov, Mohamed Azimane, José Pineda de Gyvez, Manoj Sachdev

Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Analysis and Design of LVTSCR-based EOS/ESD Protection Circuits for Burn-in Environment.

Oleg Semenov, Hossein Sarbishaei, Manoj Sachdev

Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

A 0.8V Delta-Sigma modulator using DTMOS technique.

Mohammad Maymandi-Nejad, Manoj Sachdev

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Programmable techniques for cell stability test and debug in embedded SRAMs.

Andrei Pavlov, Manoj Sachdev, José Pineda de Gyvez, Mohamed Azimane

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2004

Correction to "A Digitally Programmable Delay Element: Design and Analysis".

Mohammad Maymandi-Nejad, Manoj Sachdev

IEEE Trans. Very Large Scale Integr. Syst., 2004

A low-power reduced swing global clocking methodology.

Farhad H. A. Asgari, Manoj Sachdev

IEEE Trans. Very Large Scale Integr. Syst., 2004

The Impact of CMOS technology scaling on MOSFETs second breakdown: Evaluation of ESD robustness.

Oleg Semenov, Hossein Sarbishaei, Valery Axelrad, Manoj Sachdev

Microelectron. Reliab., 2004

Evaluation of STI degradation using temperature dependence of leakage current in parasitic STI MOSFET.

Oleg Semenov, Michael S. Obrecht, Manoj Sachdev

Microelectron. Reliab., 2004

An analytical equation for the oscillation frequency of high-frequency ring oscillators.

Stephen Docking, Manoj Sachdev

IEEE J. Solid State Circuits, 2004

DFT for Delay Fault Testing of High-Performance Digital Circuits.

Bhaskar Chatterjee, Manoj Sachdev, Ali Keshavarzi

IEEE Des. Test Comput., 2004

AN SRAM Weak Cell Fault Model and a DFT Technique with a Programmable Detection Threshold.

Andrei Pavlov, Manoj Sachdev, José Pineda de Gyvez

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

A DFT Technique for Delay Fault Testability and Diagnostics in 32-Bit High Performance CMOS ALUs.

Bhaskar Chatterjee, Manoj Sachdev, Ali Keshavarzi

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Leakage Control Techniques for Designing Robust, Low Power Wide-OR Domino Logic for sub-130 nm CMOS Technologies.

Bhaskar Chatterjee, Manoj Sachdev, Ram Krishnamurthy

Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004

An Overview of Substrate Noise Reduction Techniques.

Shahab Ardalan, Manoj Sachdev

Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004

Efficient adaptive voltage scaling system through on-chip critical path emulation.

Mohamed Elgebaly, Manoj Sachdev

Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004

A CPL-based dual supply 32-bit ALU for sub 180nm CMOS technologies.

Bhaskar Chatterjee, Manoj Sachdev, Ram Krishnamurthy

Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004

Low power dual matchline ternary content addressable memory.

Nitin Mohan, Manoj Sachdev

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Modeling and designing energy-delay optimized wide domino circuits.

Christine Kwong, Bhaskar Chatterjee, Manoj Sachdev

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Design optimizations for microprocessors at low temperature.

Arman Vassighi, Ali Keshavarzi, Siva G. Narendra, Gerhard Schrom, Yibin Ye, Seri Lee, Greg Chrysler, Manoj Sachdev, Vivek De

Proceedings of the 41th Design Automation Conference, 2004

2003

A digitally programmable delay element: design and analysis.

Mohammad Maymandi-Nejad, Manoj Sachdev

IEEE Trans. Very Large Scale Integr. Syst., 2003

Testing high-performance pipelined circuits with slow-speed testers.

Muhammad Nummer, Manoj Sachdev

ACM Trans. Design Autom. Electr. Syst., 2003

Leakage Current in Sub-Quarter Micron MOSFET: A Perspective on Stressed Delta <i>I</i>_DDQ Testing.

Oleg Semenov, Arman Vassighi, Manoj Sachdev

J. Electron. Test., 2003

A DFT Technique for Testing High-Speed Circuits with Arbitrarily Slow Testers.

Muhammad Nummer, Manoj Sachdev

J. Electron. Test., 2003

Transistor-Level Fault Analysis and Test Algorithm Development for Ternary Dynamic Content Addressable Memorie.

Derek Wright, Manoj Sachdev

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Burn-in Temperature Projections for Deep Sub-micron Technologies.

Oleg Semenov, Arman Vassighi, Manoj Sachdev, Ali Keshavarzi, Charles F. Hawkins

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Effectiveness and scaling trends of leakage control techniques for sub-130nm CMOS technologies.

Bhaskar Chatterjee, Manoj Sachdev, Steven Hsu, Ram Krishnamurthy, Shekhar Borkar

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

Thermal Management of High Performance Microprocessors.

Arman Vassighi, Oleg Semenov, Manoj Sachdev, Ali Keshavarzi

Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

DFT for Testing igh-Performance Pipelined Circuits with Slow-Speed Testers.

Muhammad Nummer, Manoj Sachdev

Proceedings of the 2003 Design, 2003

2002

A comparative analysis of low-power low-voltage dual-edge-triggered flip-flops.

Wai Chung, Timothy Lo, Manoj Sachdev

IEEE Trans. Very Large Scale Integr. Syst., 2002

Leakage and Process Variation Effects in Current Testing on Future CMOS Circuits.

Ali Keshavarzi, James W. Tschanz, Siva G. Narendra, Vivek De, W. Robert Daasch, Kaushik Roy, Manoj Sachdev, Charles F. Hawkins

IEEE Des. Test Comput., 2002

Trends and Challenges in VLSI Technology Scaling towards 100nm (Tutorial Abstract).

Stefan Rusu, Manoj Sachdev, Christer Svensson, Bram Nauta

Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

Multi-Gigahertz Digital Test Challenges and Techniques.

Manoj Sachdev

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

A DFT Technique for Low Frequency Delay Fault Testing in High Performance Digital Circuits.

Bhaskar Chatterjee, Manoj Sachdev, Ali Keshavarzi

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Effect of Static Power Dissipation in Burn-In Environment on Yield of VLSI.

Arman Vassighi, Oleg Semenov, Manoj Sachdev, Ali Keshavarzi

Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002

2001

Design for Delay Testability in High-Speed Digital ICs.

Hans G. Kerkhoff, Han Speek, M. Shashani, Manoj Sachdev

J. Electron. Test., 2001

Current-Based Testing for Deep-Submicron VLSIs.

Manoj Sachdev

IEEE Des. Test Comput., 2001

A Methodology for Testing High-Performance Circuits at Arbitrarily Low Test Frequency.

Muhammad Nummer, Manoj Sachdev

Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

Comparative delay and energy of single edge-triggered & dual edge-triggered pulsed flip-flops for high-performance microprocessors.

James W. Tschanz, Siva G. Narendra, Zhanping Chen, Shekhar Borkar, Manoj Sachdev, Vivek De

Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

2000

A Low-Speed BIST Framework for High-Performance Circuit Testing.

Hans G. Kerkhoff, Mansour Shashaani, Manoj Sachdev

Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

Multiple-parameter CMOS IC testing with increased sensitivity for I_DDQ.

Ali Keshavarzi, Kaushik Roy, Charles F. Hawkins, Manoj Sachdev, Krishnamurthy Soumyanath, Vivek De

Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

Bridging the testing speed gap: design for delay testability.

Han Speek, Hans G. Kerkhoff, Manoj Sachdev, Mansour Shashaani

Proceedings of the 5th European Test Workshop, 2000

1999

Off-Chip Diagnosis of Aperture Jitter in Full-Flash Analog-to-Digital Converters.

Richard Rosing, Hans G. Kerkhoff, Ronald J. W. T. Tangelder, Manoj Sachdev

J. Electron. Test., 1999

Configurations for IDDQ-Testable PLAs.

Manoj Sachdev, Hans G. Kerkhoff

IEEE Des. Test Comput., 1999

A DFT technique for high performance circuit testing.

Mansour Shashaani, Manoj Sachdev

Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

1998

Defect detection with transient current testing and its potential for deep sub-micron CMOS ICs.

Manoj Sachdev, Peter Janssen, Victor Zieren

Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

1997

Open Defects in CMOS RAM Address Decoders.

Manoj Sachdev

IEEE Des. Test Comput., 1997

Deep sub-micron I_DDQ testing: issues and solutions.

Manoj Sachdev

Proceedings of the European Design and Test Conference, 1997

1996

Separate<i>I</i>_DDQ testing of signal and bias paths in CMOS ICs for defect diagnosis.

Manoj Sachdev

J. Electron. Test., 1996

Deep Sub-micron I_DDQ Test Options.

Manoj Sachdev

Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

Low power, testable dual edge triggered flip-flops.

Rafael Llopis, Manoj Sachdev

Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996

Test and Testability Techniques for Open Defects in RAM Address Decoders.

Manoj Sachdev

Proceedings of the 1996 European Design and Test Conference, 1996

1995

A realistic defect oriented testability methodology for analog circuits.

Manoj Sachdev

J. Electron. Test., 1995

Reducing the CMOS RAM test complexity with<i>I</i>_DDQ and voltage testing.

Manoj Sachdev

J. Electron. Test., 1995

Testing Defects in Scan Chains.

Manoj Sachdev

IEEE Des. Test Comput., 1995

Industrial Relevance of Analog IFA: A Fact or a Fiction.

Manoj Sachdev, Bert Atzema

Proceedings of the Proceedings IEEE International Test Conference 1995, 1995

I_DDQ and Voltage Testable CMOS Flip-flop Configurations.

Manoj Sachdev

Proceedings of the Proceedings IEEE International Test Conference 1995, 1995

Defect-oriented test methodology for complex mixed-signal circuits.

F. C. M. Kuijstermans, Manoj Sachdev, A. P. Thijssen

Proceedings of the 1995 European Design and Test Conference, 1995

1994

Transforming Sequential Logic in Digital CMOS ICs for Voltage and IDDQ Testing.

Manoj Sachdev

Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

1993

Development of Fault Model and Test Algorithms for Embedded DRAMs.

Manoj Sachdev, Math Verstraelen

Proceedings of the Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics, 1993

Catastrophic Defects Oriented Testability Analysis of a Class AB Amplifier.

Manoj Sachdev

Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1993