Dhruv Patel

According to our database, Dhruv Patel authored at least 5 papers between 2018 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

A 112-Gb/s - 8.2-dBm Sensitivity 4-PAM Linear TIA in 16-nm CMOS With Co-Packaged Photodiodes.

Dhruv Patel, Alireza Sharif Bakhtiar, Tony Chan Carusone

IEEE J. Solid State Circuits, March, 2023

2022

A 112 Gb/s -8.2 dBm Sensitivity 4-PAM Linear TIA in 16nm CMOS with Co-Packaged Photodiodes.

Dhruv Patel, Alireza Sharif Bakhtiar, Anthony Chan Carusone

Proceedings of the IEEE Custom Integrated Circuits Conference, 2022

2021

Body Biased Sense Amplifier With Auto-Offset Mitigation for Low-Voltage SRAMs.

Dhruv Patel, Adam Neale, Derek Wright, Manoj Sachdev

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

2019

Hybrid Latch-Type Offset Tolerant Sense Amplifier for Low-Voltage SRAMs.

Dhruv Patel, Adam Neale, Derek Wright, Manoj Sachdev

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

2018

Sense amplifier offset characterisation and test implications for low-voltage SRAMs in 65 nm.

Dhruv Patel, Derek Wright, Manoj Sachdev

Proceedings of the 23rd IEEE European Test Symposium, 2018