Vineet Sahula
Orcid: 0000-0001-9431-4518
According to our database1,
Vineet Sahula
authored at least 40 papers
between 2001 and 2023.
Collaborative distances:
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Bibliography
2023
Filtering and Extended Vocabulary based Translation for Low-resource Language Pair of Sanskrit-Hindi.
ACM Trans. Asian Low Resour. Lang. Inf. Process., April, 2023
Enhanced Multicore Performance Using Novel Thread-Aware Cache Coherence and Prefetch-Control Mechanism.
IEEE Embed. Syst. Lett., March, 2023
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2023
2022
Variability aware Golden Reference Free methodology for Hardware Trojan Detection Using Robust Delay Analysis.
CoRR, 2022
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2022
2021
SRCP: sharing and reuse-aware replacement policy for the partitioned cache in multicore systems.
Des. Autom. Embed. Syst., 2021
Cogn. Comput. Syst., 2021
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2021
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2021
2020
An Augmented Translation Technique for low Resource language pair: Sanskrit to Hindi translation.
CoRR, 2020
Stochastic Automata Network for Performance Evaluation of Heterogeneous SoC Communication.
CoRR, 2020
Intensifying Challenge Obfuscation by Cascading FPGA RO-PUFs for Random Number Generation.
Proceedings of the 33rd International Conference on VLSI Design and 19th International Conference on Embedded Systems, 2020
2019
Correction to: Novel Randomized Placement for FPGA Based Robust ROPUF with Improved Uniqueness.
J. Electron. Test., 2019
J. Electron. Test., 2019
Novel Randomized & Biased Placement for FPGA Based Robust Random Number Generator with Enhanced Uniqueness.
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019
Proceedings of the 9th International Symposium on Embedded Computing and System Design, 2019
Device Design Space Exploration of Thin Film Hydrogen Sensor Based on Macro-model Generated Using Machine Learning.
Proceedings of the 2019 IEEE SENSORS, Montreal, QC, Canada, October 27-30, 2019, 2019
2018
Novel Variability Aware Path Selection for Self-Referencing Based Hardware Trojan Detection.
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018
2016
IEEE Trans. Circuits Syst. II Express Briefs, 2016
Accurate and Efficient Estimation of Dynamic Virtual Ground Voltage in Power Gated Circuits.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016
Golden IC free methodology for hardware Trojan detection using symmetric path delays.
Proceedings of the 20th International Symposium on VLSI Design and Test, 2016
Proceedings of the 2016 International Conference on Advances in Computing, 2016
Proceedings of the 2016 International Conference on Advances in Computing, 2016
2015
Probabilistic model for nanocell reliability evaluation in presence of transient errors.
IET Comput. Digit. Tech., 2015
Proceedings of the 19th International Symposium on VLSI Design and Test, 2015
Proceedings of the 2015 International Conference on Advances in Computing, 2015
2014
Hybrid image fusion scheme using self-fractional Fourier functions and multivariate empirical mode decomposition.
Signal Process., 2014
Features classification using geometrical deformation feature vector of support vector machine and active appearance algorithm for automatic facial expression recognition.
Mach. Vis. Appl., 2014
ACM J. Emerg. Technol. Comput. Syst., 2014
2013
Energy Aware Task Scheduling for Soft Real Time Systems using an Analytical Approach for Energy Estimation
CoRR, 2013
Architectural Level Sub-threshold Leakage Power Estimation of SRAM Arrays with its Peripherals.
Proceedings of the VLSI Design and Test, 17th International Symposium, 2013
Proceedings of the VLSI Design and Test, 17th International Symposium, 2013
2012
Features classification using support vector machine for a facial expression recognition system.
J. Electronic Imaging, 2012
Power Aware Hardware Prototyping of Multiclass SVM Classifier Through Reconfiguration.
Proceedings of the 25th International Conference on VLSI Design, 2012
2011
Proceedings of the UKSim 5th European Symposium on Computer Modeling and Simulation, 2011
2010
Stochastic Automata Network Based Approach for Performance Evaluation of Network-on-Chip Communication Architecture.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010
2008
Interactive Generalized Semi Markov Process Model for Evaluating Arbitration Schemes of SoC Bus Architectures.
Proceedings of the EMS 2008, 2008
2002
Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002
2001
The Hierarchical Concurrent Flow Graph Approach for Modeling and Analysis of Design Processes.
Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001