Di Li

According to our database1, Di Li authored at least 16 papers between 2010 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.



In proceedings 
PhD thesis 


Online presence:

On csauthors.net:


High Resolution ADC for Ultrasound Color Doppler Imaging Based on MASH Sigma-Delta Modulator.
IEEE Trans. Biomed. Eng., 2020

A 20-MHz BW MASH Sigma-Delta Modulator with Mismatch Noise Randomization for Multi-Bit DACs.
J. Circuits Syst. Comput., 2020

An optimized fully-passive noise-shaping SAR ADC with integration capacitor reuse technique.
IEICE Electron. Express, 2020

A 6-bit digital CMOS variable gain attenuator with large dynamic range and high linearity-in-dB for ultrasound imaging applications.
Microelectron. J., 2019

Mismatch errors randomization for multi-bit DAC in sigma-delta modulators based on butterfly-type network.
Microelectron. J., 2019

A 15-MHz bandwidth double sampling MASH25b-15b sigma-delta modulator with DEM for multibit DACs.
Int. J. Circuit Theory Appl., 2019

A large dynamic range voltage controlled attenuator with improved linearity-in-dB for ultrasound applications.
Int. J. Circuit Theory Appl., 2019

Design of a fully integrated receiver analog baseband chain for 2.4-GHz ZigBee applications.
Microelectron. J., 2016

A Power-Efficient Compact Pipelined ADC for ZigBee Receiver Applications.
J. Circuits Syst. Comput., 2016

A large dynamic-range, high dB-linearity VGA using switch arrays and second-order mismatch-shaping DEM technique.
Int. J. Circuit Theory Appl., 2016

An IM2-free floating current buffer using average power based automatic calibration for IEEE 802.15.6 transmitter.
IEICE Electron. Express, 2016

A 5-GHz LC VCO with digital AAC and AFBS for 2.4 GHz ZigBee transceiver applications.
Microelectron. J., 2015

A low-distortion multi-bit sigma-delta ADC with mismatch-shaping DACs for WLAN applications.
Microelectron. J., 2015

A fully integrated feedback AGC loop for ZigBee (IEEE 802.15.4) RF transceiver applications.
Microelectron. J., 2014

Design of a Fully Integrated 2.4 GHz frequency PLL synthesizer for ZigBee Transceiver Application.
J. Circuits Syst. Comput., 2014

Design of a low power GPS receiver in 0.18 µm CMOS technology with a SigmaDeltafractional-N synthesizer.
J. Zhejiang Univ. Sci. C, 2010