Di Wu

Orcid: 0000-0001-9775-8026

Affiliations:
  • University of Wisconsin-Madison, Madison, WI, USA
  • Fudan University, State Key Laboratory of Application Specific Integrated Circuit & System, Shanghai, China (former)


According to our database1, Di Wu authored at least 17 papers between 2013 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

Online presence:

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Bibliography

2024
Carat: Unlocking Value-Level Parallelism for Multiplier-Free GEMMs.
Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2024

2022
uBrain: a unary brain computer interface.
Proceedings of the ISCA '22: The 49th Annual International Symposium on Computer Architecture, New York, New York, USA, June 18, 2022

uSystolic: Byte-Crawling Unary Systolic Array.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2022

2021
uGEMM: Unary Computing for GEMM Applications.
IEEE Micro, 2021

In-Stream Correlation-Based Division and Bit-Inserting Square Root in Stochastic Computing.
IEEE Des. Test, 2021

UNO: Virtualizing and Unifying Nonlinear Operations for Emerging Neural Networks.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2021

Special Session: When Dataflows Converge: Reconfigurable and Approximate Computing for Emerging Neural Networks.
Proceedings of the 39th IEEE International Conference on Computer Design, 2021

Normalized Stability: A Cross-Level Design Metric for Early Termination in Stochastic Computing.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020
UGEMM: Unary Computing Architecture for GEMM Applications.
Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020

2019
SECO: A Scalable Accuracy Approximate Exponential Function Via Cross-Layer Optimization.
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019

In-Stream Stochastic Division and Square Root via Correlation.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2016
Strategies for Reducing Decoding Cycles in Stochastic LDPC Decoders.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

Convergence-optimized variable node structure for stochastic LDPC decoder.
Proceedings of the 2016 IEEE International Conference on Acoustics, 2016

2015
Latency-optimized stochastic LDPC decoder for high-throughput applications.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

An area-efficient architecture for stochastic LDPC decoder.
Proceedings of the 2015 IEEE International Conference on Digital Signal Processing, 2015

2014
An Efficient Multirate LDPC-CC Decoder With a Layered Decoding Algorithm for the IEEE 1901 Standard.
IEEE Trans. Circuits Syst. II Express Briefs, 2014

2013
A high-throughput LDPC decoder for optical communication.
Proceedings of the IEEE 10th International Conference on ASIC, 2013


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