Xiaoyang Zeng

IEEE Trans. Image Process., 2023

TSDN: Two-Stage Raw Denoising in the Dark.

[BibT_eX]

[DOI]

IEEE Trans. Image Process., 2023

A 1T2R1C ReRAM CIM Accelerator With Energy-Efficient Voltage Division and Capacitive Coupling for CNN Acceleration in AI Edge Applications.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2023

A 40nm 150 TOPS/W High Row-Parallel MRAM Compute-in-Memory Macro with Series 3T1MTJ Bitcell for MAC Operation.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

Queue-based Spatiotemporal Filter and Clustering for Dynamic Vision Sensor.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

Fast VVC Intra Encoding for Video Coding for Machines.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

Denoising Method for Dynamic Vision Sensor Based on Two-Dimensional Event Density.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

Graph-Attention-Network-Based Cost Estimation Model in Materialized View Environment.

[BibT_eX]

[DOI]

Proceedings of the 29th IEEE International Conference on Parallel and Distributed Systems, 2023

An Efficient Bundle Adjustment Approach for Stereo Visual Odometry with Pose Consensus.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Consumer Electronics, 2023

A 2MHz-BW 96.8dB-SNDR 98dB-SNR CT-Zoom ADC With Residue Feedforward, Redundancy and Fully LMS-Based Calibration.

[BibT_eX]

[DOI]

Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023

A Self Bias-flip Piezoelectric Energy Harvester Array without External Energy Reservoirs achieving 488% Improvement with 4-Ratio Switched-PEH DC-DC Converter.

[BibT_eX]

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2023

Multi-Instance Bias Suppression for Enhanced Generalization in Breast Cancer Diagnosis : Harnessing Histopathological Big Data Insights.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Big Data, 2023

GCFP-ACIM: A 40nm 4.74TFLOPS/W General Complex Float-Point Analog Compute-in-Memory with Adaptive Power-Saving for HDR Signal Processing Applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023

A Decision-Based CORDIC Hardware for Arc Tangent Calculation.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Conference on ASIC, 2023

Performance Error Evaluation of gem5 Simulator for ARM Server.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Conference on ASIC, 2023

Bit-Offsetter: A Bit-serial DNN Accelerator with Weight-offset MAC for Bit-wise Sparsity Exploitation.

[BibT_eX]

[DOI]

Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023

2022

Obstacle Detection for Unmanned Surface Vehicles by Fusion Refinement Network.

[BibT_eX]

[DOI]

Weina Zhou

Xinxin Huang

IEICE Trans. Inf. Syst., August, 2022

Tear the Image Into Strips for Style Transfer.

[BibT_eX]

[DOI]

IEEE Trans. Multim., 2022

QA-Filter: A QP-Adaptive Convolutional Neural Network Filter for Video Coding.

[BibT_eX]

[DOI]

IEEE Trans. Image Process., 2022

A High Throughput and Energy Efficient Lepton Hardware Encoder With Hash-Based Memory Optimization.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. Video Technol., 2022

A Fast CABAC Hardware Design for Accelerating the Rate Estimation in HEVC.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. Video Technol., 2022

Piezoelectric Energy Harvesters: An Overview on Design Strategies and Topologies.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2022

Hardware-Efficient Beamspace Direction-of-Arrival Estimator for Unequal-Sized Subarrays.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2022

Completely Blind Video Quality Evaluator.

[BibT_eX]

[DOI]

IEEE Signal Process. Lett., 2022

A 2D2R ReRAM CIM accelerator for multilayer perceptron in visual classification applications.

[BibT_eX]

[DOI]

Microelectron. J., 2022

An Attention Nested U-Structure Suitable for Salient Ship Detection in Complex Maritime Environment.

[BibT_eX]

[DOI]

Weina Zhou

Ying Zhou

IEICE Trans. Inf. Syst., 2022

An Efficient Low-Complexity Convolutional Neural Network Filter.

[BibT_eX]

[DOI]

IEEE Multim., 2022

A 28 nm 81 Kb 59-95.3 TOPS/W 4T2R ReRAM Computing-in-Memory Accelerator With Voltage-to-Time-to-Digital Based Output.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., 2022

A high accuracy and low complexity quality control method for image compression.

[BibT_eX]

[DOI]

CoRR, 2022

FAVER: Blind Quality Prediction of Variable Frame Rate Videos.

[BibT_eX]

[DOI]

CoRR, 2022

Learning from the NN-based Compressed Domain with Deep Feature Reconstruction Loss.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Visual Communications and Image Processing, 2022

COMB-MCM: Computing-on-Memory-Boundary NN Processor with Bipolar Bitwise Sparsity Optimization for Scalable Multi-Chiplet-Module Edge Machine Learning.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2022

An Enhanced Start-up Circuit Eliminating All Trojan States in Self-biased Reference Generators.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

A Multiple Charge Extractions and Multiple Precharge Interface Circuit for Piezoelectric Energy Harvesting.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

A Synthesis Friendly Dynamic Amplifier with Fuzzy-Logic Piecewise-Linear Calibration.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

A Cross Regulation Reduced Multi-Output and Multi-VCR Piezoelectric Energy Harvesting System Using Shared Capacitors.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

NIMBLE: A Neuromorphic Learning Scheme and Memristor Based Computing-in-Memory Engine for EMG Based Hand Gesture Recognition.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

A QP-adaptive Mechanism for CNN-based Filter in Video Coding.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

A Low-latency Carrier Phase Recovery Hardware for Coherent Optical Communication.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

A Fully Synthesizable Dynamic Latched Comparator with Reduced Kickback Noise.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

A High Area-Efficiency RRAM-Based Strong PUF with Multi-Entropy Source and Configurable Double-Read Process.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Fast Intra Mode Decision for VVC Based on Histogram of Oriented Gradient.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

A 3.1 Gbin/s advanced entropy coding hardware design for AVS3.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Blind Video Quality Assessment via Space-Time Slice Statistics.

[BibT_eX]

[DOI]

Proceedings of the 2022 IEEE International Conference on Image Processing, 2022

Learned Video Compression With Residual Prediction And Feature-Aided Loop Filter.

[BibT_eX]

[DOI]

Proceedings of the 2022 IEEE International Conference on Image Processing, 2022

No-Reference Quality Assessment of Variable Frame-Rate Videos Using Temporal Bandpass Statistics.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Acoustics, 2022

A 130μW Three-Step DT Incremental Δ ∑ ADC Achieving 107.6dB DR and 99.3dB SNDR with Zoom and Extended-Range Counting.

[BibT_eX]

[DOI]

Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022

A 91.6% Peak Efficiency Time-Domain-Controlled Single-Inductor Triple-Output Step-Up Converter with ±7.5 to ±12V Bipolar Output Voltages.

[BibT_eX]

[DOI]

Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022

A 1.8GΩ-Input-Impedance 0.15µV-Input-Referred-Ripple Chopper Amplifier with Local Positive Feedback and SAR-Assisted Ripple Reduction.

[BibT_eX]

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2022

An Approximate-Computing-Based Adaptive Equalizer for Polarization Mode Dispersion.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022

An Improved Multi-Objective Optimization Framework for Soft-Error Immune Circuits.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022

2021

Unambiguous Direction-of-Arrival Estimation for Improved Scanning Efficiency in Subarray-Based Hybrid Array.

[BibT_eX]

[DOI]

Ziyu Guo

Xiaodong Wang

IEEE Trans. Veh. Technol., 2021

An Energy Efficient Computing-in-Memory Accelerator With 1T2R Cell and Fully Analog Processing for Edge AI Applications.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2021

General Efficient TMR for Combinational Circuit Hardening Against Soft Errors and Improved Multi-Objective Optimization Framework.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Radiation Hardened 12T SRAM With Crossbar-Based Peripheral Circuit in 28nm CMOS Technology.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

MC-LSTM: Real-Time 3D Human Action Detection System for Intelligent Healthcare Applications.

[BibT_eX]

[DOI]

IEEE Trans. Biomed. Circuits Syst., 2021

Learned Image Compression With Separate Hyperprior Decoders.

[BibT_eX]

[DOI]

IEEE Open J. Circuits Syst., 2021

A 28 nm, 397 μW real-time dynamic gesture recognition chip based on RISC-V processor.

[BibT_eX]

[DOI]

Microelectron. J., 2021

An energy-efficient crypto-extension design for RISC-V.

[BibT_eX]

[DOI]

Microelectron. J., 2021

Synthesizable lead-lag quantization technique for digital VCO-based ΔΣ ADC.

[BibT_eX]

[DOI]

Microelectron. J., 2021

A low-power twiddle factor addressing architecture for split-radix FFT processor.

[BibT_eX]

[DOI]

Microelectron. J., 2021

High-Density 3-D Stackable Crossbar 2D2R nvTCAM With Low-Power Intelligent Search for Fast Packet Forwarding in 5G Applications.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2021

Orthogonal obfuscation based key management for multiple IP protection.

[BibT_eX]

[DOI]

Integr., 2021

Manifold constrained joint sparse learning via non-convex regularization.

[BibT_eX]

[DOI]

Neurocomputing, 2021

A Reconfigurable 74-140Mbps LDPC Decoding System for CCSDS Standard.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2021

Learned Video Compression with Residual Prediction and Loop Filter.

[BibT_eX]

[DOI]

CoRR, 2021

A Power and Area Efficient Lepton Hardware Encoder with Hash-based Memory Optimization.

[BibT_eX]

[DOI]

CoRR, 2021

An efficient non-convex total variation approach for image deblurring and denoising.

[BibT_eX]

[DOI]

Appl. Math. Comput., 2021

Decision Tree-Based Adaptive Reconfigurable Cache Scheme.

[BibT_eX]

[DOI]

Wei Zhu

Algorithms, 2021

Fast Style Transfer with High Shape Retention.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Fast Object Detection in HEVC Intra Compressed Domain.

[BibT_eX]

[DOI]

Proceedings of the 29th European Signal Processing Conference, 2021

TRIGON: A Single-phase-clocking Low Power Hardened Flip-Flop with Tolerance to Double-Node-Upset for Harsh Environments Applications.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

A-A KD: Attention and Activation Knowledge Distillation.

[BibT_eX]

[DOI]

Proceedings of the Seventh IEEE International Conference on Multimedia Big Data, 2021

A Synthesizable 0.0060mm2 VCO-Based Delta Sigma Modulator with Digital Tri-level Feedback Scheme.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021

Mutli-level Regression Anchor-free Object Detection.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Conference on ASIC, 2021

Intra-array Non-Idealities Modeling and Algorithm Optimization for RRAM-based Computing-in-Memory Applications.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Conference on ASIC, 2021

A High-Efficient and Configurable Hardware Accelerator for Convolutional Neural Network.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Conference on ASIC, 2021

Small Object Detection in Aerial Images.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Conference on ASIC, 2021

A Fine-grained Sparse Neural Network Accelerator for Image Classification.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Conference on ASIC, 2021

A Heterogeneous HEVC Video Encoder System Based on Two-Level CPU-FPGA Computing Architecture.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Conference on ASIC, 2021

A 0.9V Supply 12.5Gb/s LVDS Receiver in 28nm CMOS Process.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Conference on ASIC, 2021

Combining Max Pooling and ReLU Activation Function in Stochastic Computing.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Conference on ASIC, 2021

Arbitrary Style Transfer via Learning to Paint in the Feature Domain.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Conference on ASIC, 2021

An 8Kb 40-nm 2T2MTJ STT-MRAM Design with 2.6ns Access Time and Time-Adjustable Writing Process.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Conference on ASIC, 2021

A Multiplier-less Transform Architecture with the Diagonal Data Mapping Transpose Memory for The AVS3 Standard.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Conference on ASIC, 2021

An Efficient Markov Random Field Based Denoising Approach for Dynamic Vision Sensor.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Conference on ASIC, 2021

Knowledge Distillation for U-Net Based Image Denoising.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Conference on ASIC, 2021

2020

A Power Analysis Attack Resistant Multicore Platform With Effective Randomization Techniques.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2020

Radiation-Hardened 0.3-0.9-V Voltage-Scalable 14T SRAM and Peripheral Circuit in 28-nm Technology for Space Applications.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2020

QNet: An Adaptive Quantization Table Generator Based on Convolutional Neural Network.

[BibT_eX]

[DOI]

IEEE Trans. Image Process., 2020

A Pipelined 2D Transform Architecture Supporting Mixed Block Sizes for the VVC Standard.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. Video Technol., 2020

A High-Performance Stochastic LDPC Decoder Architecture Designed via Correlation Analysis.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst., 2020

VPQC: A Domain-Specific Vector Processor for Post-Quantum Cryptography Based on RISC-V Architecture.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2020

A Robust Hardened Latch Featuring Tolerance to Double-Node-Upset in 28nm CMOS for Spaceborne Application.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2020

Piezoelectric Energy-Harvesting Interface Using Split-Phase Flipping-Capacitor Rectifier With Capacitor Reuse for Input Power Adaptation.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2020

A Highly Configurable 7.62GOP/s Hardware Implementation for LSTM.

[BibT_eX]

[DOI]

IEICE Trans. Electron., 2020

A Communication-Aware DNN Accelerator on ImageNet Using In-Memory Entry-Counting Based Algorithm-Circuit-Architecture Co-Design in 65-nm CMOS.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., 2020

A Convolutional Neural Network-Based Low Complexity Filter.

[BibT_eX]

[DOI]

CoRR, 2020

A 28nm 1.5Mb Embedded 1T2R RRAM with 14.8 Mb/mm2 using Sneaking Current Suppression and Compensation Techniques.

[BibT_eX]

[DOI]

Proceedings of the IEEE Symposium on VLSI Circuits, 2020

A Synthesis Friendly VCO-Based Delta-Sigma ADC with Process Variation Tolerance.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

An Energy Harvesting System with Reconfigurable Piezoelectric Energy Harvester Array for IoT Applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Directly Obtaining Matching Points without Keypoints for Image Stitching.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Single Image Dehazing using a Novel Histogram Tranformation Network.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Design Methodology of Clock Polarity Inversion Technique for Frequency Dividers.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

A Learning-Based Low Complexity in-Loop Filter for Video Coding.

[BibT_eX]

[DOI]

Proceedings of the 2020 IEEE International Conference on Multimedia & Expo Workshops, 2020

A Hardware Friendly Haze Removal Method and Its Implementation.

[BibT_eX]

[DOI]

Proceedings of the 2020 IEEE International Conference on Consumer Electronics (ICCE), 2020

Exploring a Bayesian Optimization Framework Compatible with Digital Standard Flow for Soft-Error-Tolerant Circuit.

[BibT_eX]

[DOI]

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

Context Event Features and Event Embedding Enhanced Event Detection.

[BibT_eX]

[DOI]

Proceedings of the ACAI 2020: 3rd International Conference on Algorithms, 2020

2019

A 2-D Predistortion Based on Profile Inversion for Fully Digital Cartesian Transmitter.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2019

Column-Selection-Enabled 10T SRAM Utilizing Shared Diff-VDD Write and Dropped-VDD Read for Power Reduction.

[BibT_eX]

[DOI]

Liang Wen

Yuejun Zhang

IEEE Trans. Very Large Scale Integr. Syst., 2019

Recursive Synaptic Bit Reuse: An Efficient Way to Increase Memory Capacity in Associative Memory.

[BibT_eX]

[DOI]

Mingoo Seok

IEEE Trans. Very Large Scale Integr. Syst., 2019

A Real-Time and Hardware-Efficient Processor for Skeleton-Based Action Recognition With Lightweight Convolutional Neural Network.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2019

Recursive Binary Neural Network Training Model for Efficient Usage of On-Chip Memory.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

A Micro-Code-Based IME Engine for HEVC and Its Hardware Implementation.

[BibT_eX]

[DOI]

IEICE Trans. Electron., 2019

A 24-bit sigma-delta ADC with configurable chopping scheme.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2019

Pixels and Panoramas: An Enhanced Cubic Mapping Scheme for Video\/Image-Based Virtual-Reality Scenes.

[BibT_eX]

[DOI]

IEEE Consumer Electron. Mag., 2019

ManiDec: Manifold Constrained Low-Rank and Sparse Decomposition.

[BibT_eX]

[DOI]

IEEE Access, 2019

A Compact 32-Pixel TU-Oriented and SRAM-Free Intra Prediction VLSI Architecture for HEVC Decoder.

[BibT_eX]

[DOI]

Genwei Tang

IEEE Access, 2019

A Micro-Code-Based Hardware Architecture of Integer Motion Estimation for HEVC.

[BibT_eX]

[DOI]

Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019

Adaptive CU Split Decision with Pooling-variable CNN for VVC Intra Encoding.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE Visual Communications and Image Processing, 2019

Fast QTMT Partition Decision Algorithm in VVC Intra Coding based on Variance and Gradient.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE Visual Communications and Image Processing, 2019

A Minimal Adder-oriented 1D DST-VII/DCT-VIII Hardware Implementation for VVC Standard.

[BibT_eX]

[DOI]

Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019

Dual Learning-based Video Coding with Inception Dense Blocks.

[BibT_eX]

[DOI]

Proceedings of the Picture Coding Symposium, 2019

A Piezoelectric Energy-Harvesting Interface Using Split-Phase Flipping-Capacitor Rectifier and Capacitor Reuse Multiple-VCR SC DC-DC Achieving 9.3× Energy-Extraction Improvement.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid- State Circuits Conference, 2019

A 32-Pixel IDCT-Adapted HEVC Intra Prediction VLSI Architecture.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Acoustic Frequency Division Based on Active Metamaterial: An Experimental Demonstration of Acoustic Frequency Halving.

[BibT_eX]

[DOI]

Proceedings of the IoT as a Service - 5th EAI International Conference, 2019

Bayesian Face Recognition Approach Based on Feature Fusion.

[BibT_eX]

[DOI]

Proceedings of the Advances in Natural Computation, Fuzzy Systems and Knowledge Discovery - Proceedings of the 15th International Conference on Natural Computation, Fuzzy Systems and Knowledge Discovery (ICNC-FSKD 2019), Kunming, China, July 20-22, 2019, 2019

Very Deep Residual Network for Image Matting.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE International Conference on Image Processing, 2019

A Skeleton-based Action Recognition System for Medical Condition Detection.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE Biomedical Circuits and Systems Conference, 2019

A 3.01 mm2 65.38Gb/s Stochastic LDPC Decoder for IEEE 802.3an in 65 nm.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019

A 28nm 512Kb adjacent 2T2R RRAM PUF with interleaved cell mirroring and self-adaptive splitting for extremely low bit error rate of cryptographic key.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019

A Hardware-efficient Accelerator for Encoding Stage of Text-to-speech Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Conference on ASIC, 2019

Enhanced Recursive Residual Network for Single Image Super-Resolution.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Conference on ASIC, 2019

High throughput multi-code LDPC encoder for CCSDS standard.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Conference on ASIC, 2019

Nonvolatile Binary CNN Accelerator with Extremely Low Standby Power using RRAM for IoT Applications.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Conference on ASIC, 2019

An Orthogonal Algorithm for Key Management in Hardware Obfuscation.

[BibT_eX]

[DOI]

Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2019

2018

A Hardware-Oriented IME Algorithm for HEVC and Its Hardware Implementation.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. Video Technol., 2018

Countering power analysis attacks by exploiting characteristics of multicore processors.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2018

A 15 W wireless power receiver with an improved full-wave synchronous rectifier.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2018

A single-supply sub-threshold level shifter with an internal supply feedback loop for multi-voltage applications.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2018

Multi-mode Study of Deep Learning Applications in Acoustic Signal Processing.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE International Workshop on Signal Processing Systems, 2018

The Hardware Acceleration of SC Decoder for Polar Code towards HLS Optimization.

[BibT_eX]

[DOI]

Proceedings of the International SoC Design Conference, 2018

An Automatic Task Partition Method for Multi-core System.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

A Compact and Configurable Long Short-Term Memory Neural Network Hardware Architecture.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE International Conference on Image Processing, 2018

MiniTracker: A Lightweight CNN-based System for Visual Object Tracking on Embedded Device.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE International Conference on Digital Signal Processing, 2018

A High-Throughput QC-LDPC Decoder for Near-Earth Application.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE International Conference on Digital Signal Processing, 2018

Panoramic video delivery based on Laplace compensation and Sphere-Markov probability model.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Consumer Electronics, 2018

Content adaptive tiling method based on user access preference for streaming panoramic video.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Consumer Electronics, 2018

Dynamic Task Scheduler for Real Time Requirement in Cloud Computing System.

[BibT_eX]

[DOI]

Proceedings of the Algorithms and Architectures for Parallel Processing, 2018

Nonvolatile Crossbar 2D2R TCAM with Cell Size of 16.3 F2 and K-means Clustering for Power Reduction.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

2017

Sub-threshold level converter with internal supply feedback for multi-voltage applications.

[BibT_eX]

[DOI]

Liang Wen

Haibo Wen

IET Circuits Devices Syst., 2017

A High-Throughput and Compact Hardware Implementation for the Reconstruction Loop in HEVC Intra Encoding.

[BibT_eX]

[DOI]

IEICE Trans. Electron., 2017

A multi-core-based heterogeneous parallel turbo decoder.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2017

Recursive Binary Neural Network Learning Model with 2.28b/Weight Storage Requirement.

[BibT_eX]

[DOI]

Mingoo Seok

CoRR, 2017

Instruction set extension and hardware acceleration for SVM application toward a vector processor.

[BibT_eX]

[DOI]

Proceedings of the International SoC Design Conference, 2017

An efficient spherical video sampling scheme based on Cube model.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Consumer Electronics, 2017

Extending memory capacity of neural associative memory based on recursive synaptic bit reuse.

[BibT_eX]

[DOI]

Mingoo Seok

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

FPGA-based efficient implementation of SURF algorithm.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International Conference on ASIC, 2017

Parallel implementations of SHA-3 on a 24-core processor with software and hardware co-design.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International Conference on ASIC, 2017

Fp2 arithmetic acceleration based on modified Barrett modular multiplication algorithm.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International Conference on ASIC, 2017

Research of a reconfigurable coarse-grained cryptographic processing unit based on different operation similar structure.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International Conference on ASIC, 2017

A high utilization FPGA-based accelerator for variable-scale convolutional neural network.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International Conference on ASIC, 2017

A configurable nonlinear operation unit for neural network accelerator.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International Conference on ASIC, 2017

Implementation of a pipeline division-free MMSE MIMO detector that support soft-input and soft-output.

[BibT_eX]

[DOI]

Proceedings of the 23rd Asia-Pacific Conference on Communications, 2017

2016

A Combined Deblocking Filter and SAO Hardware Architecture for HEVC.

[BibT_eX]

[DOI]

IEEE Trans. Multim., 2016

Strategies for Reducing Decoding Cycles in Stochastic LDPC Decoders.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2016

Bit-Interleaving-Enabled 8T SRAM With Shared Data-Aware Write and Reference-Based Sense Amplifier.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2016

Subthreshold Level Shifter With Self-Controlled Current Limiter by Detecting Output Error.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2016

An Area-Efficient Error-Resilient Ultralow-Power Subthreshold ECG Processor.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2016

Analysis and improvement of ramp gain error in single-ramp single-slope ADCs for CMOS image sensors.

[BibT_eX]

[DOI]

Xu Cheng

Qi Feng

Microelectron. J., 2016

Cryptographie coprocessor design for IoT sensor nodes.

[BibT_eX]

[DOI]

Proceedings of the International SoC Design Conference, 2016

Neural network based seizure detection system using raw EEG data.

[BibT_eX]

[DOI]

Proceedings of the International SoC Design Conference, 2016

Quarter LCU based integer motion estimation algorithm for HEVC.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Conference on Image Processing, 2016

Convergence-optimized variable node structure for stochastic LDPC decoder.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Conference on Acoustics, 2016

A low-cost and energy-efficient EEG processor for continuous seizure detection using wavelet transform and AdaBoost.

[BibT_eX]

[DOI]

Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2016

2015

Design and Analysis of Highly Energy/Area-Efficient Multiported Register Files With Read Word-Line Sharing Strategy in 65-nm CMOS Process.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

A 65 nm Cryptographic Processor for High Speed Pairing Computation.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

In-Block Prediction-Based Mixed Lossy and Lossless Reference Frame Recompression for Next-Generation Video Encoding.

[BibT_eX]

[DOI]

Qing Shang

IEEE Trans. Circuits Syst. Video Technol., 2015

An Energy-Efficient Design for ECG Recording and R-Peak Detection Based on Wavelet Transform.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2015

A Heterogeneous Multicore Crypto-Processor With Flexible Long-Word-Length Computation.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2015

A Parallel-Access Mapping Method for the Data Exchange Buffers Around DCT/IDCT in HEVC Encoders Based on Single-Port SRAMs.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2015

A 1.5-D Multi-Channel EEG Compression Algorithm Based on NLSPIHT.

[BibT_eX]

[DOI]

IEEE Signal Process. Lett., 2015

A low cost architecture for high performance face detection.

[BibT_eX]

[DOI]

Weina Zhou

Huafeng Wu

Microprocess. Microsystems, 2015

Non-binary digital calibration for split-capacitor DAC in SAR ADC.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2015

A High-Throughput Processor for Dual-Field Elliptic Curve Cryptography with Power Analysis Resistance.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE 12th Intl Conf on Ubiquitous Intelligence and Computing and 2015 IEEE 12th Intl Conf on Autonomic and Trusted Computing and 2015 IEEE 15th Intl Conf on Scalable Computing and Communications and Its Associated Workshops (UIC-ATC-ScalCom), 2015

EM independent Gaussian approximate message passing and its application in OFDM impulsive noise mitigation.

[BibT_eX]

[DOI]

Proceedings of the 28th IEEE International System-on-Chip Conference, 2015

An implementation of turbo equalization using cyclic prefix in LTE downlink system.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE Workshop on Signal Processing Systems, 2015

Latency-optimized stochastic LDPC decoder for high-throughput applications.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A high-throughput HEVC deblocking filter VLSI architecture for 8k×4k application.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

An area-efficient architecture for stochastic LDPC decoder.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Conference on Digital Signal Processing, 2015

Iterative disparity voting based stereo matching algorithm and its hardware implementation.

[BibT_eX]

[DOI]

Zhi Hu

Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

A configurable SoC design for information security.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

A low-cost SoC implementation of AES algorithm for bio-signals.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

Energy-efficient sub-threshold level shifter.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

Parallel implementation of AES on 2.5D multicore platform with hardware and software co-design.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

A SIMD multiplier-accumulator design for pairing cryptography.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

Motion artifact removal based on ICA for ambulatory ECG monitoring.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

A lifting-based 2-D discrete wavelet transform architecture for data compression of bio-potential signals.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

A flexible HEVC intra mode decision hardware for 8kx4k real time encoder.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

OFDM synchronization implementation based on Chisel platform for 5G research.

[BibT_eX]

[DOI]

Ziqiang Li

Yun Chen

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

A SRAM-saving two-stage storage strategy for the coefficients memories in HEVC encoders.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

Exploration for energy-efficient ECC decoder of WBAN.

[BibT_eX]

[DOI]

Jun Han

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2014

Single-Port SRAM-Based Transpose Memory With Diagonal Data Mapping for Large Size 2-D DCT/IDCT.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2014

An Efficient Implementation of Montgomery Multiplication on Multicore Platform With Optimized Algorithm, Task Partitioning, and Network Architecture.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2014

Low-Power Multicore Processor Design With Reconfigurable Same-Instruction Multiple Process.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2014

A 16-Core Processor With Shared-Memory and Message-Passing Communications.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2014

An Efficient Multirate LDPC-CC Decoder With a Layered Decoding Algorithm for the IEEE 1901 Standard.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2014

Analysis of a read disturb-free 9T SRAM cell with bit-interleaving capability.

[BibT_eX]

[DOI]

Microelectron. J., 2014

An area-efficient dual replica-bitline delay technique for process-variation-tolerant low voltage SRAM sense amplifier timing.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2014

A hardware-friendly method for rate-distortion optimization of HEVC intra coding.

[BibT_eX]

[DOI]

Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014

Acceleration of Naive-Bayes algorithm on multicore processor for massive text classification.

[BibT_eX]

[DOI]

Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

An error-resilient wavelet-based ECG processor under voltage overscaling.

[BibT_eX]

[DOI]

Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2014

2013

Parallelization of Radix-2 Montgomery Multiplication on Multicore Platform.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2013

Accurate Sampling Timing Acquisition for Baseband OFDM Power-Line Communication in Non-Gaussian Noise.

[BibT_eX]

[DOI]

IEEE Trans. Commun., 2013

An Ultra-Low Power QRS Complex Detection Algorithm Based on Down-Sampling Wavelet Transform.

[BibT_eX]

[DOI]

IEEE Signal Process. Lett., 2013

A 960 μW 10-bit 70-MS/s SAR ADC with an energy-efficient capacitor-switching scheme.

[BibT_eX]

[DOI]

Yue Wu

Xu Cheng

Microelectron. J., 2013

A Unified Forward/Inverse Transform Architecture for Multi-Standard Video Codec Design.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

A 1.5 Gb/s Highly Parallel Turbo Decoder for 3GPP LTE/LTE-Advanced.

[BibT_eX]

[DOI]

IEICE Trans. Commun., 2013

A pipelined VLSI architecture for Sample Adaptive Offset (SAO) filter and deblocking filter of HEVC.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2013

Robustness Analysis of Mesh-Based Network-on-Chip Architecture under Flooding-Based Denial of Service Attacks.

[BibT_eX]

[DOI]

Proceedings of the IEEE Eighth International Conference on Networking, 2013

Fine residual carrier frequency and sampling frequency estimation in wireless OFDM systems.

[BibT_eX]

[DOI]

Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

Algorithm and VLSI architecture of channel estimation impaired by impulsive noise in PLC.

[BibT_eX]

[DOI]

Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

A 65nm 39GOPS/W 24-core processor with 11Tb/s/W packet-controlled circuit-switched double-layer network-on-chip and heterogeneous execution array.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

A low power register file with asynchronously controlled read-isolation and software-directed write-discarding.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

A 3.4dB NF k-band LNA in 65nm CMOS technology.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

A split-capacitor vcm-based capacitor-switching scheme for low-power SAR ADCs.

[BibT_eX]

[DOI]

Yue Wu

Xu Cheng

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

A high-throughput VLSI architecture for deblocking filter in HEVC.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Time-Division-Multiplexer based routing algorithm for NoC system.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Implementation and optimization of 3780-point FFT on multi-core system.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

An efficient multi-rate LDPC-CC decoder with layered decoding algorithm.

[BibT_eX]

[DOI]

Proceedings of IEEE International Conference on Communications, 2013

A 920MHz quad-core cryptography processor accelerating parallel task processing of public-key algorithms.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

A highly energy-efficient compressed sensing encoder with robust subthreshold clockless pipeline for wireless BANs.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE Biomedical Circuits and Systems Conference (BioCAS), Rotterdam, The Netherlands, October 31, 2013

H.264 video parallel decoder on a 24-core processor.

[BibT_eX]

[DOI]

Proceedings of the IEEE 10th International Conference on ASIC, 2013

A 2D mesh NoC with self-configurable and shared-FIFOs routers.

[BibT_eX]

[DOI]

Proceedings of the IEEE 10th International Conference on ASIC, 2013

MCVP-NoC: Many-Core Virtual Platform with Networks-on-Chip support.

[BibT_eX]

[DOI]

Proceedings of the IEEE 10th International Conference on ASIC, 2013

A turbo decoder implementation for LTE downlink mapped on a multi-core processor platform.

[BibT_eX]

[DOI]

Proceedings of the IEEE 10th International Conference on ASIC, 2013

Efficient implementation of 3780-point FFT on a 16-core processor.

[BibT_eX]

[DOI]

Proceedings of the IEEE 10th International Conference on ASIC, 2013

Low power design for FIR filter.

[BibT_eX]

[DOI]

Proceedings of the IEEE 10th International Conference on ASIC, 2013

A high-throughput LDPC decoder for optical communication.

[BibT_eX]

[DOI]

Proceedings of the IEEE 10th International Conference on ASIC, 2013

A fast multi-core virtual platform and its application on software development.

[BibT_eX]

[DOI]

Proceedings of the IEEE 10th International Conference on ASIC, 2013

A 1.8-V 14-bit inverter-based incremental ΣΔ ADC for CMOS image sensor.

[BibT_eX]

[DOI]

Proceedings of the IEEE 10th International Conference on ASIC, 2013

An extensible and real-time compressive sensing reconstruction hardware for WBANs using OMP.

[BibT_eX]

[DOI]

Proceedings of the IEEE 10th International Conference on ASIC, 2013

A fast 8×8 IDCT algorithm for HEVC.

[BibT_eX]

[DOI]

Proceedings of the IEEE 10th International Conference on ASIC, 2013

A highly pipelined VLSI architecture for all modes and block sizes intra prediction in HEVC encoder.

[BibT_eX]

[DOI]

Proceedings of the IEEE 10th International Conference on ASIC, 2013

A hybrid router combining circuit switching and packet switching with virtual channels for on-chip networks.

[BibT_eX]

[DOI]

Proceedings of the IEEE 10th International Conference on ASIC, 2013

Highly flexible WBAN transmit-receive system based on USRP.

[BibT_eX]

[DOI]

Jun Han

Proceedings of the IEEE 10th International Conference on ASIC, 2013

Design of a high throughput configurable variable-length FFT processor based on switch network architecture.

[BibT_eX]

[DOI]

Proceedings of the IEEE 10th International Conference on ASIC, 2013

Positionable wearable fall detection system for elderly assisted living applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE 10th International Conference on ASIC, 2013

An ultra low-power and area-efficient baseband processor for WBAN transmitter.

[BibT_eX]

[DOI]

Proceedings of the Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, 2013

A hardware-efficient variable-length FFT processor for low-power applications.

[BibT_eX]

[DOI]

Proceedings of the Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, 2013

2012

An Area-Efficient Reconfigurable LDPC Decoder with Conflict Resolution.

[BibT_eX]

[DOI]

IEICE Trans. Electron., 2012

A High Speed Reconfigurable Face Detection Architecture Based on AdaBoost Cascade Algorithm.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2012

Design Approach and Implementation of Application Specific Instruction Set Processor for SHA-3 BLAKE Algorithm.

[BibT_eX]

[DOI]

IEICE Trans. Electron., 2012

A 64 Cycles/MB, Luma-Chroma Parallelized H.264/AVC Deblocking Filter for 4 K × 2 K Applications.

[BibT_eX]

[DOI]

Weiwei Shen

IEICE Trans. Electron., 2012

A Flexible LDPC Decoder Architecture Supporting TPMP and TDMP Decoding Algorithms.

[BibT_eX]

[DOI]

Shuangqu Huang

Yun Chen

IEICE Trans. Inf. Syst., 2012

A Fully Programmable Reed-Solomon Decoder on a Multi-Core Processor Platform.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2012

An 8 × 4 Adaptive Hadamard Transform Based FME VLSI Architecture for 4 K × 2 K H.264/AVC Encoder.

[BibT_eX]

[DOI]

IEICE Trans. Electron., 2012

Efficient Implementation of OFDM Inner Receiver on a Programmable Multi-Core Processor Platform.

[BibT_eX]

[DOI]

IEICE Trans. Commun., 2012

A Flexible Architecture for TURBO and LDPC Codes.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012

A 64×32bit 4-read 2-write low power and area efficient register file in 65nm CMOS.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2012

Fine Residual Carrier Frequency and Sampling Frequency Estimation in Wireless OFDM Systems

[BibT_eX]

[DOI]

Chen Chen

Yun Chen

CoRR, 2012

A Low Complexity Macroblock Layer Rate Control Scheme Base on Weighted-Window for H.264 Encoder.

[BibT_eX]

[DOI]

Proceedings of the Advances in Multimedia Modeling - 18th International Conference, 2012

An 800MHz 320mW 16-core processor with message-passing and shared-memory inter-core communication mechanisms.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

A low-cost architecture for multi-mode Reed-Solomon decoder.

[BibT_eX]

[DOI]

Proceedings of the International SoC Design Conference, 2012

A multi-core mapping implementation of 3780-point FFT.

[BibT_eX]

[DOI]

Proceedings of the International SoC Design Conference, 2012

Task-binding based branch-and-bound algorithm for NoC mapping.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

A parallel CAVLC design for 4096×2160p encoder.

[BibT_eX]

[DOI]

Huibo Zhong

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

A pure software ldpc decoder on a multi-core processor platform with reduced inter-processor communication cost.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Evaluating performance of manycore processors with various granularities considering yield and lifetime reliability.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

An improved coarse synchronization scheme in 3GPP LTE downlink OFDM systems.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

A Unified 4/8/16/32-Point Integer IDCT Architecture for Multiple Video Coding Standards.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Conference on Multimedia and Expo, 2012

A 60mW baseband SoC for CMMB receiver.

[BibT_eX]

[DOI]

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

A 16-pixel parallel architecture with block-level/mode-level co-reordering approach for intra prediction in 4k×2k H.264/AVC video encoder.

[BibT_eX]

[DOI]

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

A single-routing layered LDPC decoder for 10Gbase-T Ethernet in 130nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

A low power ASIP for precision configurable FFT processing.

[BibT_eX]

[DOI]

Proceedings of the Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, 2012

2011

An 847-955 Mb/s 342-397 mW Dual-Path Fully-Overlapped QC-LDPC Decoder for WiMAX System in 0.13 μ m CMOS.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2011

Efficient Iterative Frequency Domain Equalization for Single Carrier System with Insufficient Cyclic Prefix.

[BibT_eX]

[DOI]

IEICE Trans. Commun., 2011

A Scalable and Reconfigurable Fault-Tolerant Distributed Routing Algorithm for NoCs.

[BibT_eX]

[DOI]

Zewen Shi

Zhiyi Yu

IEICE Trans. Inf. Syst., 2011

Optimized 2-D SAD Tree Architecture of Integer Motion Estimation for H.264/AVC.

[BibT_eX]

[DOI]

Satoshi Goto

IEICE Trans. Electron., 2011

A 4-way parallel CAVLC design for H.264/AVC 4Kx2K 60fps encoder.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2011

MUX-MCM based quantization VLSI architecture for H.264/AVC high profile encoder.

[BibT_eX]

[DOI]

Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

A full-mode FME VLSI architecture based on 8×8/4×4 adaptive Hadamard Transform for QFHD H.264/AVC encoder.

[BibT_eX]

[DOI]

Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

A common flexible architecture for Turbo/LDPC codes.

[BibT_eX]

[DOI]

Proceedings of the International SoC Design Conference, 2011

Flexible and efficient FEC decoders supporting multiple transmission standards.

[BibT_eX]

[DOI]

Proceedings of the International SoC Design Conference, 2011

Fault tolerant computing for stream DSP applications using GALS multi-core processors.

[BibT_eX]

[DOI]

Zhiyi Yu

Zewen Shi

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

A channel estimation scheme for Chinese DTTB system combating long echo and high doppler shift.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

A reconfigurable and deadlock-free routing algorithm for 2D Mesh Network-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

A 4.32 mm2 170mW LDPC decoder in 0.13μm CMOS for WiMax/Wi-Fi applications.

[BibT_eX]

[DOI]

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

A high speed reconfigurable face detection architecture.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

An optimized mapping algorithm based on Simulated Annealing for regular NoC architecture.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

A two-way parallel CAVLC encoder for 4K×2K H.264/AVC.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

A low power 1.0 GHz VCO in 65nm-CMOS LP-process.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

Modified Minimal-Connected-Component fault block model to deal with defective links and nodes for 2D-mesh NoCs.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

Design of a single-ended cell based 65nm 32×32b 4R2W register file.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

A security processor based on MIPS 4KE architecture.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

A method of quadratic programming for mapping on NoC architecture.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

A hardware/software co-design approach for multiple-standard video bitstream parsing.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

A low power 10-bit 100-MS/s SAR ADC in 65nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

Analysis of adaptive support-weight based stereo matching for hardware realization.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

A multi-mode 1-V DAC+filter in 65-nm CMOS for reconfigurable (GSM, TD-SCDMA and WCDMA) transmitters.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

A NoC-based multi-core architecture for IEEE 802.11i CCMP.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

A channel estimator for LTE downlink mapped on a multi-core processor platform.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

A control scheme for a 65nm 32×32b 4-read 2-write register file.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

A robust frame synchronization scheme for Broadband Power-line Communication.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

Modeling of a double-sampling switched-capacitor bandpass delta-sigma modulator for multi-standard applications.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

An area-Efficient LDPC decoder for multi-standard with conflict resolution.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE International Conference on Application-specific Systems, 2011

2010

An Area-Efficient and Low-Power Multirate Decoder for Quasi-Cyclic Low-Density Parity-Check Codes.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2010

An efficient iterative frequency domain equalization for ATSC DTV receiver.

[BibT_eX]

[DOI]

IEEE Trans. Consumer Electron., 2010

Low cost VLSI architecture of resisting long echo channel estimation for DTMB system.

[BibT_eX]

[DOI]

IEEE Trans. Consumer Electron., 2010

Programmable Architecture for Flexi-Mode QC-LDPC Decoder Supporting Wireless LAN/MAN Applications and Beyond.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2010

A Cost-Efficient LDPC Decoder for DVB-S2 with the Solution to Address Conflict Issue.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

Optimized digital automatic gain control for DVB-S2 system.

[BibT_eX]

[DOI]

Proceedings of the 2010 Wireless Telecommunications Symposium, 2010

Robust and reliable frame synchronization method for DVB-S2 system.

[BibT_eX]

[DOI]

Proceedings of the 2010 Wireless Telecommunications Symposium, 2010

A scalable and fault-tolerant routing algorithm for NoCs.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

A 128/256-point pipeline FFT/IFFT processor for MIMO OFDM system IEEE 802.16e.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

A flexible LDPC decoder architecture supporting two decoding algorithms.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

A fully-overlapped multi-mode QC-LDPC decoder architecture for mobile WiMAX applications.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE International Conference on Application-specific Systems Architectures and Processors, 2010

2009

A multi-task-oriented security processing architecture with powerful extensibility.

[BibT_eX]

[DOI]

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008

Low-cost reconfigurable VLSI architecture for fast fourier transform.

[BibT_eX]

[DOI]

IEEE Trans. Consumer Electron., 2008

A 1.8-V 22-mW 10-bit 30-MS/s Pipelined CMOS ADC for Low-Power Subsampling Applications.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2008

Low-complexity two-stage timing acquisition scheme for UWB communications.

[BibT_eX]

[DOI]

Yanjie Peng

Lang Mai

Proceedings of the Wireless Telecommunications Symposium, 2008

Tracking loop for IR-UWB communications in IEEE 802.15 multi-path channels.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Optimal frame synchronization for DVB-S2.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

A full-custom design of AES SubByte module with signal independent power consumption.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

A low-cost cryptographic processor for security embedded system.

[BibT_eX]

[DOI]

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007

Robust Timing and Frequency Synchronization Scheme for DTMB System.

[BibT_eX]

[DOI]

IEEE Trans. Consumer Electron., 2007

A Novel Five-Point Algorithm of Phase Noise Cancellation in DTMB.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

Two-dimensional Parity-based Concurrent Error Detection Method for AES Algorithm against Differential Fault Attack and its VLSI Implementation.

[BibT_eX]

[DOI]

Proceedings of the IEEE Workshop on Signal Processing Systems, 2007

An Energy-Proportion Synchronization Method for IR-UWB Communications.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

A Low-cost and High-performance SoC Design for OMA DRM2 Applications.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006

Adaptive bandwidth PLL with compact current mode filter.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A new dual-field elliptic curve cryptography processor.

[BibT_eX]

[DOI]

Yongyi Wu