Xiaoyang Zeng

According to our database1, Xiaoyang Zeng authored at least 201 papers between 2005 and 2019.

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Bibliography

2019
A 2-D Predistortion Based on Profile Inversion for Fully Digital Cartesian Transmitter.
IEEE Trans. VLSI Syst., 2019

Column-Selection-Enabled 10T SRAM Utilizing Shared Diff-VDD Write and Dropped-VDD Read for Power Reduction.
IEEE Trans. VLSI Syst., 2019

Recursive Synaptic Bit Reuse: An Efficient Way to Increase Memory Capacity in Associative Memory.
IEEE Trans. VLSI Syst., 2019

Pixels and Panoramas: An Enhanced Cubic Mapping Scheme for Video\/Image-Based Virtual-Reality Scenes.
IEEE Consumer Electronics Magazine, 2019

A Piezoelectric Energy-Harvesting Interface Using Split-Phase Flipping-Capacitor Rectifier and Capacitor Reuse Multiple-VCR SC DC-DC Achieving 9.3× Energy-Extraction Improvement.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2018
A Hardware-Oriented IME Algorithm for HEVC and Its Hardware Implementation.
IEEE Trans. Circuits Syst. Video Techn., 2018

Countering power analysis attacks by exploiting characteristics of multicore processors.
IEICE Electronic Express, 2018

A 15 W wireless power receiver with an improved full-wave synchronous rectifier.
IEICE Electronic Express, 2018

A single-supply sub-threshold level shifter with an internal supply feedback loop for multi-voltage applications.
IEICE Electronic Express, 2018

Multi-mode Study of Deep Learning Applications in Acoustic Signal Processing.
Proceedings of the 2018 IEEE International Workshop on Signal Processing Systems, 2018

The Hardware Acceleration of SC Decoder for Polar Code towards HLS Optimization.
Proceedings of the International SoC Design Conference, 2018

An Automatic Task Partition Method for Multi-core System.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

A Compact and Configurable Long Short-Term Memory Neural Network Hardware Architecture.
Proceedings of the 2018 IEEE International Conference on Image Processing, 2018

MiniTracker: A Lightweight CNN-based System for Visual Object Tracking on Embedded Device.
Proceedings of the 23rd IEEE International Conference on Digital Signal Processing, 2018

A High-Throughput QC-LDPC Decoder for Near-Earth Application.
Proceedings of the 23rd IEEE International Conference on Digital Signal Processing, 2018

Panoramic video delivery based on Laplace compensation and Sphere-Markov probability model.
Proceedings of the IEEE International Conference on Consumer Electronics, 2018

Content adaptive tiling method based on user access preference for streaming panoramic video.
Proceedings of the IEEE International Conference on Consumer Electronics, 2018

Dynamic Task Scheduler for Real Time Requirement in Cloud Computing System.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2018

Nonvolatile Crossbar 2D2R TCAM with Cell Size of 16.3 F2 and K-means Clustering for Power Reduction.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

2017
Sub-threshold level converter with internal supply feedback for multi-voltage applications.
IET Circuits, Devices & Systems, 2017

A High-Throughput and Compact Hardware Implementation for the Reconstruction Loop in HEVC Intra Encoding.
IEICE Transactions, 2017

A multi-core-based heterogeneous parallel turbo decoder.
IEICE Electronic Express, 2017

Instruction set extension and hardware acceleration for SVM application toward a vector processor.
Proceedings of the International SoC Design Conference, 2017

An efficient spherical video sampling scheme based on Cube model.
Proceedings of the IEEE International Conference on Consumer Electronics, 2017

Extending memory capacity of neural associative memory based on recursive synaptic bit reuse.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

FPGA-based efficient implementation of SURF algorithm.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

Parallel implementations of SHA-3 on a 24-core processor with software and hardware co-design.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

Fp2 arithmetic acceleration based on modified Barrett modular multiplication algorithm.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

Research of a reconfigurable coarse-grained cryptographic processing unit based on different operation similar structure.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

A high utilization FPGA-based accelerator for variable-scale convolutional neural network.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

A configurable nonlinear operation unit for neural network accelerator.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

Implementation of a pipeline division-free MMSE MIMO detector that support soft-input and soft-output.
Proceedings of the 23rd Asia-Pacific Conference on Communications, 2017

2016
A Combined Deblocking Filter and SAO Hardware Architecture for HEVC.
IEEE Trans. Multimedia, 2016

Strategies for Reducing Decoding Cycles in Stochastic LDPC Decoders.
IEEE Trans. on Circuits and Systems, 2016

Bit-Interleaving-Enabled 8T SRAM With Shared Data-Aware Write and Reference-Based Sense Amplifier.
IEEE Trans. on Circuits and Systems, 2016

Subthreshold Level Shifter With Self-Controlled Current Limiter by Detecting Output Error.
IEEE Trans. on Circuits and Systems, 2016

An Area-Efficient Error-Resilient Ultralow-Power Subthreshold ECG Processor.
IEEE Trans. on Circuits and Systems, 2016

Analysis and improvement of ramp gain error in single-ramp single-slope ADCs for CMOS image sensors.
Microelectronics Journal, 2016

Cryptographie coprocessor design for IoT sensor nodes.
Proceedings of the International SoC Design Conference, 2016

Neural network based seizure detection system using raw EEG data.
Proceedings of the International SoC Design Conference, 2016

Quarter LCU based integer motion estimation algorithm for HEVC.
Proceedings of the 2016 IEEE International Conference on Image Processing, 2016

Convergence-optimized variable node structure for stochastic LDPC decoder.
Proceedings of the 2016 IEEE International Conference on Acoustics, 2016

A low-cost and energy-efficient EEG processor for continuous seizure detection using wavelet transform and AdaBoost.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2016

2015
Design and Analysis of Highly Energy/Area-Efficient Multiported Register Files With Read Word-Line Sharing Strategy in 65-nm CMOS Process.
IEEE Trans. VLSI Syst., 2015

A 65 nm Cryptographic Processor for High Speed Pairing Computation.
IEEE Trans. VLSI Syst., 2015

In-Block Prediction-Based Mixed Lossy and Lossless Reference Frame Recompression for Next-Generation Video Encoding.
IEEE Trans. Circuits Syst. Video Techn., 2015

An Energy-Efficient Design for ECG Recording and R-Peak Detection Based on Wavelet Transform.
IEEE Trans. on Circuits and Systems, 2015

A Heterogeneous Multicore Crypto-Processor With Flexible Long-Word-Length Computation.
IEEE Trans. on Circuits and Systems, 2015

A Parallel-Access Mapping Method for the Data Exchange Buffers Around DCT/IDCT in HEVC Encoders Based on Single-Port SRAMs.
IEEE Trans. on Circuits and Systems, 2015

A 1.5-D Multi-Channel EEG Compression Algorithm Based on NLSPIHT.
IEEE Signal Process. Lett., 2015

A low cost architecture for high performance face detection.
Microprocessors and Microsystems - Embedded Hardware Design, 2015

Non-binary digital calibration for split-capacitor DAC in SAR ADC.
IEICE Electronic Express, 2015

A High-Throughput Processor for Dual-Field Elliptic Curve Cryptography with Power Analysis Resistance.
Proceedings of the 2015 IEEE 12th Intl Conf on Ubiquitous Intelligence and Computing and 2015 IEEE 12th Intl Conf on Autonomic and Trusted Computing and 2015 IEEE 15th Intl Conf on Scalable Computing and Communications and Its Associated Workshops (UIC-ATC-ScalCom), 2015

EM independent Gaussian approximate message passing and its application in OFDM impulsive noise mitigation.
Proceedings of the 28th IEEE International System-on-Chip Conference, 2015

An implementation of turbo equalization using cyclic prefix in LTE downlink system.
Proceedings of the 2015 IEEE Workshop on Signal Processing Systems, 2015

Latency-optimized stochastic LDPC decoder for high-throughput applications.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A high-throughput HEVC deblocking filter VLSI architecture for 8k×4k application.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

An area-efficient architecture for stochastic LDPC decoder.
Proceedings of the 2015 IEEE International Conference on Digital Signal Processing, 2015

Iterative disparity voting based stereo matching algorithm and its hardware implementation.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

A configurable SoC design for information security.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

A low-cost SoC implementation of AES algorithm for bio-signals.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

Energy-efficient sub-threshold level shifter.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

Parallel implementation of AES on 2.5D multicore platform with hardware and software co-design.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

A SIMD multiplier-accumulator design for pairing cryptography.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

Motion artifact removal based on ICA for ambulatory ECG monitoring.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

A lifting-based 2-D discrete wavelet transform architecture for data compression of bio-potential signals.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

A flexible HEVC intra mode decision hardware for 8kx4k real time encoder.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

OFDM synchronization implementation based on Chisel platform for 5G research.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

A SRAM-saving two-stage storage strategy for the coefficients memories in HEVC encoders.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

Exploration for energy-efficient ECC decoder of WBAN.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2014
Single-Port SRAM-Based Transpose Memory With Diagonal Data Mapping for Large Size 2-D DCT/IDCT.
IEEE Trans. VLSI Syst., 2014

An Efficient Implementation of Montgomery Multiplication on Multicore Platform With Optimized Algorithm, Task Partitioning, and Network Architecture.
IEEE Trans. VLSI Syst., 2014

Low-Power Multicore Processor Design With Reconfigurable Same-Instruction Multiple Process.
IEEE Trans. on Circuits and Systems, 2014

A 16-Core Processor With Shared-Memory and Message-Passing Communications.
IEEE Trans. on Circuits and Systems, 2014

An Efficient Multirate LDPC-CC Decoder With a Layered Decoding Algorithm for the IEEE 1901 Standard.
IEEE Trans. on Circuits and Systems, 2014

Analysis of a read disturb-free 9T SRAM cell with bit-interleaving capability.
Microelectronics Journal, 2014

An area-efficient dual replica-bitline delay technique for process-variation-tolerant low voltage SRAM sense amplifier timing.
IEICE Electronic Express, 2014

A hardware-friendly method for rate-distortion optimization of HEVC intra coding.
Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014

Acceleration of Naive-Bayes algorithm on multicore processor for massive text classification.
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

An error-resilient wavelet-based ECG processor under voltage overscaling.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2014

2013
Parallelization of Radix-2 Montgomery Multiplication on Multicore Platform.
IEEE Trans. VLSI Syst., 2013

Accurate Sampling Timing Acquisition for Baseband OFDM Power-Line Communication in Non-Gaussian Noise.
IEEE Trans. Communications, 2013

An Ultra-Low Power QRS Complex Detection Algorithm Based on Down-Sampling Wavelet Transform.
IEEE Signal Process. Lett., 2013

A 960 μW 10-bit 70-MS/s SAR ADC with an energy-efficient capacitor-switching scheme.
Microelectronics Journal, 2013

A Unified Forward/Inverse Transform Architecture for Multi-Standard Video Codec Design.
IEICE Transactions, 2013

A 1.5 Gb/s Highly Parallel Turbo Decoder for 3GPP LTE/LTE-Advanced.
IEICE Transactions, 2013

A pipelined VLSI architecture for Sample Adaptive Offset (SAO) filter and deblocking filter of HEVC.
IEICE Electronic Express, 2013

Robustness Analysis of Mesh-Based Network-on-Chip Architecture under Flooding-Based Denial of Service Attacks.
Proceedings of the IEEE Eighth International Conference on Networking, 2013

A 65nm 39GOPS/W 24-core processor with 11Tb/s/W packet-controlled circuit-switched double-layer network-on-chip and heterogeneous execution array.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

A low power register file with asynchronously controlled read-isolation and software-directed write-discarding.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

A 3.4dB NF k-band LNA in 65nm CMOS technology.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

A split-capacitor vcm-based capacitor-switching scheme for low-power SAR ADCs.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

A high-throughput VLSI architecture for deblocking filter in HEVC.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Time-Division-Multiplexer based routing algorithm for NoC system.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Implementation and optimization of 3780-point FFT on multi-core system.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

An efficient multi-rate LDPC-CC decoder with layered decoding algorithm.
Proceedings of IEEE International Conference on Communications, 2013

A 920MHz quad-core cryptography processor accelerating parallel task processing of public-key algorithms.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

A highly energy-efficient compressed sensing encoder with robust subthreshold clockless pipeline for wireless BANs.
Proceedings of the 2013 IEEE Biomedical Circuits and Systems Conference (BioCAS), Rotterdam, The Netherlands, October 31, 2013

H.264 video parallel decoder on a 24-core processor.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

A 2D mesh NoC with self-configurable and shared-FIFOs routers.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

MCVP-NoC: Many-Core Virtual Platform with Networks-on-Chip support.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

A turbo decoder implementation for LTE downlink mapped on a multi-core processor platform.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

Efficient implementation of 3780-point FFT on a 16-core processor.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

Low power design for FIR filter.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

A high-throughput LDPC decoder for optical communication.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

A fast multi-core virtual platform and its application on software development.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

A 1.8-V 14-bit inverter-based incremental ΣΔ ADC for CMOS image sensor.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

An extensible and real-time compressive sensing reconstruction hardware for WBANs using OMP.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

A fast 8×8 IDCT algorithm for HEVC.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

A highly pipelined VLSI architecture for all modes and block sizes intra prediction in HEVC encoder.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

A hybrid router combining circuit switching and packet switching with virtual channels for on-chip networks.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

Highly flexible WBAN transmit-receive system based on USRP.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

Design of a high throughput configurable variable-length FFT processor based on switch network architecture.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

Positionable wearable fall detection system for elderly assisted living applications.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

An ultra low-power and area-efficient baseband processor for WBAN transmitter.
Proceedings of the Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, 2013

A hardware-efficient variable-length FFT processor for low-power applications.
Proceedings of the Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, 2013

2012
An Area-Efficient Reconfigurable LDPC Decoder with Conflict Resolution.
IEICE Transactions, 2012

A High Speed Reconfigurable Face Detection Architecture Based on AdaBoost Cascade Algorithm.
IEICE Transactions, 2012

Design Approach and Implementation of Application Specific Instruction Set Processor for SHA-3 BLAKE Algorithm.
IEICE Transactions, 2012

A 64 Cycles/MB, Luma-Chroma Parallelized H.264/AVC Deblocking Filter for 4 K × 2 K Applications.
IEICE Transactions, 2012

A Flexible LDPC Decoder Architecture Supporting TPMP and TDMP Decoding Algorithms.
IEICE Transactions, 2012

A Fully Programmable Reed-Solomon Decoder on a Multi-Core Processor Platform.
IEICE Transactions, 2012

An 8 × 4 Adaptive Hadamard Transform Based FME VLSI Architecture for 4 K × 2 K H.264/AVC Encoder.
IEICE Transactions, 2012

Efficient Implementation of OFDM Inner Receiver on a Programmable Multi-Core Processor Platform.
IEICE Transactions, 2012

A Flexible Architecture for TURBO and LDPC Codes.
IEICE Transactions, 2012

A 64×32bit 4-read 2-write low power and area efficient register file in 65nm CMOS.
IEICE Electronic Express, 2012

A Low Complexity Macroblock Layer Rate Control Scheme Base on Weighted-Window for H.264 Encoder.
Proceedings of the Advances in Multimedia Modeling - 18th International Conference, 2012

An 800MHz 320mW 16-core processor with message-passing and shared-memory inter-core communication mechanisms.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

A low-cost architecture for multi-mode Reed-Solomon decoder.
Proceedings of the International SoC Design Conference, 2012

A multi-core mapping implementation of 3780-point FFT.
Proceedings of the International SoC Design Conference, 2012

Task-binding based branch-and-bound algorithm for NoC mapping.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

A parallel CAVLC design for 4096×2160p encoder.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

A pure software ldpc decoder on a multi-core processor platform with reduced inter-processor communication cost.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Evaluating performance of manycore processors with various granularities considering yield and lifetime reliability.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

An improved coarse synchronization scheme in 3GPP LTE downlink OFDM systems.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

A Unified 4/8/16/32-Point Integer IDCT Architecture for Multiple Video Coding Standards.
Proceedings of the 2012 IEEE International Conference on Multimedia and Expo, 2012

A 60mW baseband SoC for CMMB receiver.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

A 16-pixel parallel architecture with block-level/mode-level co-reordering approach for intra prediction in 4k×2k H.264/AVC video encoder.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

A single-routing layered LDPC decoder for 10Gbase-T Ethernet in 130nm CMOS.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

A low power ASIP for precision configurable FFT processing.
Proceedings of the Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, 2012

2011
An 847-955 Mb/s 342-397 mW Dual-Path Fully-Overlapped QC-LDPC Decoder for WiMAX System in 0.13 μ m CMOS.
J. Solid-State Circuits, 2011

Efficient Iterative Frequency Domain Equalization for Single Carrier System with Insufficient Cyclic Prefix.
IEICE Transactions, 2011

A Scalable and Reconfigurable Fault-Tolerant Distributed Routing Algorithm for NoCs.
IEICE Transactions, 2011

Optimized 2-D SAD Tree Architecture of Integer Motion Estimation for H.264/AVC.
IEICE Transactions, 2011

A 4-way parallel CAVLC design for H.264/AVC 4Kx2K 60fps encoder.
IEICE Electronic Express, 2011

MUX-MCM based quantization VLSI architecture for H.264/AVC high profile encoder.
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

A full-mode FME VLSI architecture based on 8×8/4×4 adaptive Hadamard Transform for QFHD H.264/AVC encoder.
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

A common flexible architecture for Turbo/LDPC codes.
Proceedings of the International SoC Design Conference, 2011

Flexible and efficient FEC decoders supporting multiple transmission standards.
Proceedings of the International SoC Design Conference, 2011

Fault tolerant computing for stream DSP applications using GALS multi-core processors.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

A channel estimation scheme for Chinese DTTB system combating long echo and high doppler shift.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

A reconfigurable and deadlock-free routing algorithm for 2D Mesh Network-on-Chip.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

A 4.32 mm2 170mW LDPC decoder in 0.13μm CMOS for WiMax/Wi-Fi applications.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

A high speed reconfigurable face detection architecture.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

An optimized mapping algorithm based on Simulated Annealing for regular NoC architecture.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

A two-way parallel CAVLC encoder for 4K×2K H.264/AVC.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

A low power 1.0 GHz VCO in 65nm-CMOS LP-process.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

Modified Minimal-Connected-Component fault block model to deal with defective links and nodes for 2D-mesh NoCs.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

Design of a single-ended cell based 65nm 32×32b 4R2W register file.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

A security processor based on MIPS 4KE architecture.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

A method of quadratic programming for mapping on NoC architecture.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

A hardware/software co-design approach for multiple-standard video bitstream parsing.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

A low power 10-bit 100-MS/s SAR ADC in 65nm CMOS.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

Analysis of adaptive support-weight based stereo matching for hardware realization.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

A multi-mode 1-V DAC+filter in 65-nm CMOS for reconfigurable (GSM, TD-SCDMA and WCDMA) transmitters.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

A NoC-based multi-core architecture for IEEE 802.11i CCMP.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

A channel estimator for LTE downlink mapped on a multi-core processor platform.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

A control scheme for a 65nm 32×32b 4-read 2-write register file.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

A robust frame synchronization scheme for Broadband Power-line Communication.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

Modeling of a double-sampling switched-capacitor bandpass delta-sigma modulator for multi-standard applications.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

An area-Efficient LDPC decoder for multi-standard with conflict resolution.
Proceedings of the 22nd IEEE International Conference on Application-specific Systems, 2011

2010
An Area-Efficient and Low-Power Multirate Decoder for Quasi-Cyclic Low-Density Parity-Check Codes.
IEEE Trans. VLSI Syst., 2010

An efficient iterative frequency domain equalization for ATSC DTV receiver.
IEEE Trans. Consumer Electronics, 2010

Low cost VLSI architecture of resisting long echo channel estimation for DTMB system.
IEEE Trans. Consumer Electronics, 2010

Programmable Architecture for Flexi-Mode QC-LDPC Decoder Supporting Wireless LAN/MAN Applications and Beyond.
IEEE Trans. on Circuits and Systems, 2010

A Cost-Efficient LDPC Decoder for DVB-S2 with the Solution to Address Conflict Issue.
IEICE Transactions, 2010

Optimized digital automatic gain control for DVB-S2 system.
Proceedings of the 2010 Wireless Telecommunications Symposium, 2010

Robust and reliable frame synchronization method for DVB-S2 system.
Proceedings of the 2010 Wireless Telecommunications Symposium, 2010

A scalable and fault-tolerant routing algorithm for NoCs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

A 128/256-point pipeline FFT/IFFT processor for MIMO OFDM system IEEE 802.16e.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

A flexible LDPC decoder architecture supporting two decoding algorithms.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

A fully-overlapped multi-mode QC-LDPC decoder architecture for mobile WiMAX applications.
Proceedings of the 21st IEEE International Conference on Application-specific Systems Architectures and Processors, 2010

2009
A multi-task-oriented security processing architecture with powerful extensibility.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008
Low-cost reconfigurable VLSI architecture for fast fourier transform.
IEEE Trans. Consumer Electronics, 2008

Low-complexity two-stage timing acquisition scheme for UWB communications.
Proceedings of the Wireless Telecommunications Symposium, 2008

Tracking loop for IR-UWB communications in IEEE 802.15 multi-path channels.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Optimal frame synchronization for DVB-S2.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

A full-custom design of AES SubByte module with signal independent power consumption.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

A low-cost cryptographic processor for security embedded system.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007
Robust Timing and Frequency Synchronization Scheme for DTMB System.
IEEE Trans. Consumer Electronics, 2007

A Novel Five-Point Algorithm of Phase Noise Cancellation in DTMB.
IEICE Transactions, 2007

Two-dimensional Parity-based Concurrent Error Detection Method for AES Algorithm against Differential Fault Attack and its VLSI Implementation.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2007

An Energy-Proportion Synchronization Method for IR-UWB Communications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

A Low-cost and High-performance SoC Design for OMA DRM2 Applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006
Adaptive bandwidth PLL with compact current mode filter.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A new dual-field elliptic curve cryptography processor.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A new low cost and reconfigurable RSA crypto-processor.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A modified high-radix scalable Montgomery multiplier.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A 1.8-V 22-mW 10-bit 30-MS/s Subsampling Pipelined CMOS ADC.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

A high-performance platform-based SoC for information security.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005
VLSI design of a high-speed RAS crypto-processor with reconfigurable architecture.
Proceedings of the Eighth International Symposium on Signal Processing and Its Applications, 2005


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