Dileep Bhandarkar

According to our database1, Dileep Bhandarkar authored at least 23 papers between 1973 and 2009.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Awards

IEEE Fellow

IEEE Fellow 1997, "For contributions and technical leadership in the design of complex and reduced instruction set architecture and in computer system performance analysis.".

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2009
Performance analysis in the real world of on line services.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2009

2003
Billion Transistor Chips in Mainstream Enterprise Platforms of the Future.
Proceedings of the Ninth International Symposium on High-Performance Computer Architecture (HPCA'03), 2003

2002
Parallelism in Mainstream Enterprise Platforms of the Future.
Proceedings of the 2002 International Conference on Parallel Architectures and Compilation Techniques (PACT 2002), 2002

1997
RISC versus CISC: a tale of two chips.
SIGARCH Computer Architecture News, 1997

Performance Characterization of the Pentium(r) Pro Processor.
Proceedings of the 3rd IEEE Symposium on High-Performance Computer Architecture (HPCA '97), 1997

1996
Performance Characterization of the Alpha 21164 Microprocessor Using TP and SPEC Workloads.
Proceedings of the Second International Symposium on High-Performance Computer Architecture, 1996

Alpha implementations and architecture - complete reference and guide.
Digital Press, ISBN: 978-1-55558-130-5, 1996

1994
Characterization of Alpha AXP Performance Using TP and SPEC Workloads.
Proceedings of the 21st Annual International Symposium on Computer Architecture. Chicago, 1994

1991
Performance From Architecture: Comparing a RISC and CISC with Similar Hardware Organization.
Proceedings of the ASPLOS-IV Proceedings, 1991

1990
VAX Vector Architecture.
Proceedings of the 17th Annual International Symposium on Computer Architecture, 1990

High performance issue oriented architecture.
Proceedings of the Intellectual Leverage: Thirty-Fifth IEEE Computer Society International Conference, 1990

Vector extensions to the VAX architecture.
Proceedings of the Intellectual Leverage: Thirty-Fifth IEEE Computer Society International Conference, 1990

1987
VAX 8800 System Overview.
Proceedings of the COMPCON'87, 1987

1982
Architecture Management for Ensuring Software Compatibility in the VAX Family of Computers.
IEEE Computer, 1982

1981
Design Trade-Offs in VAX-11 Translation Buffer Organization.
IEEE Computer, 1981

1979
CCD Charge-Coupled Device Memories: A Perspective.
IEEE Computer, 1979

Special Feature the Impact Of Semiconductor Technology on Computer Systems.
IEEE Computer, 1979

1977
Some Performance Issues in Multiprocessor System Design.
IEEE Trans. Computers, 1977

1975
On the Performance of Magnetic Bubble Memories in Computer Systems.
IEEE Trans. Computers, 1975

Analysis of Memory Interference in Multiprocessors.
IEEE Trans. Computers, 1975

Tutorial: Computer System Advantages of Magnetic Bubble Memories.
IEEE Computer, 1975

A comparative evaluation of the cost effectiveness of computer systems (Paper Session).
Proceedings of the 1975 ACM Annual Conference, 1975

1973
Markov Chain Models for Analyzing Memory Interference in Multiprocessor Computer Systems.
Proceedings of the 1st Annual Symposium on Computer Architecture, 1973


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