Douglas W. Clark

According to our database1, Douglas W. Clark authored at least 49 papers between 1975 and 2006.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2006
Dynamic-Compiler-Driven Control for Microprocessor Energy and Performance.
IEEE Micro, 2006

2005
Formal Control Techniques for Power-Performance Management.
IEEE Micro, 2005

Tools and Applications for Large-Scale Display Walls.
IEEE Computer Graphics and Applications, 2005

A Dynamic Compilation Framework for Controlling Microprocessor Energy and Performance.
Proceedings of the 38th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-38 2005), 2005

Coordinated, distributed, formal energy management of chip multiprocessors.
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

Voltage and Frequency Control With Adaptive Reaction Time in Multiple-Clock-Domain Processors.
Proceedings of the 11th International Conference on High-Performance Computer Architecture (HPCA-11 2005), 2005

2004
Implementing branch-predictor decay using quasi-static memory cells.
TACO, 2004

Exposing Memory Access Regularities Using Object-Relative Memory Profiling.
Proceedings of the 2nd IEEE / ACM International Symposium on Code Generation and Optimization (CGO 2004), 2004

Formal online methods for voltage/frequency control in multiple clock domain microprocessors.
Proceedings of the 11th International Conference on Architectural Support for Programming Languages and Operating Systems, 2004

2002
Implementing Decay Techniques using 4T Quasi-Static Memory Cells.
Computer Architecture Letters, 2002

Managing leakage for transient data: decay and quasi-static 4T memory cells.
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

Applying Decay Strategies to Branch Predictors for Leakage Energy Savings.
Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

2001
Software Environments For Cluster-Based Display Systems.
Proceedings of the First IEEE International Symposium on Cluster Computing and the Grid (CCGrid 2001), 2001

2000
Speculative Updates of Local and Global Branch History: A Quantitative Analysis.
J. Instruction-Level Parallelism, 2000

Building and Using A Scalable Display Wall System.
IEEE Computer Graphics and Applications, 2000

Automatic alignment of high-resolution multi-projector display using an un-calibrated camera.
Proceedings of the IEEE Visualization 2000, 2000

A Taxonomy of Branch Mispredictions, and Alloyed Prediction as a Robust Solution to Wrong-History Mispredictions.
Proceedings of the 2000 International Conference on Parallel Architectures and Compilation Techniques (PACT'00), 2000

1999
Branch Prediction, Instruction-Window Size, and Cache Size: Performance Trade-Offs and Simulation Techniques.
IEEE Trans. Computers, 1999

Experience with an Adaptive Globally-Synchronizing Clock Algorithm.
SPAA, 1999

An Adaptive Globally-Synchronizing Clock Algorithm and its Implementation on a Myrinet-based PC Cluster.
Proceedings of the 1999 ACM SIGMETRICS international conference on Measurement and modeling of computer systems, 1999

Thread Scheduling for Out-of-core Applications with Memory Server on Multicomputers.
IOPADS, 1999

1998
Improving Prediction for Procedure Returns with Return-address-stack Repair Mechanisms.
Proceedings of the 31st Annual IEEE/ACM International Symposium on Microarchitecture, 1998

A Characterization of Processor Performance in the VAX-11/780.
Proceedings of the 25 Years of the International Symposia on Computer Architecture (Selected Papers)., 1998

Retrospective: Characterization of Processor Performance in the VAX-11/780.
Proceedings of the 25 Years of the International Symposia on Computer Architecture (Selected Papers)., 1998

Design Choices in the SHRIMP System: An Empirical Study.
Proceedings of the 25th Annual International Symposium on Computer Architecture, 1998

Monitoring Shared Virtual Memory Performance on a Myrinet-based PC Cluster.
Proceedings of the 12th international conference on Supercomputing, 1998

Multipath Execution: Opportunities and Limits.
Proceedings of the 12th international conference on Supercomputing, 1998

Performance Issues of a Distributed Frame Buffer on a Multicomputer.
Proceedings of the 1998 ACM SIGGRAPH/EUROGRAPHICS Workshop on Graphics Hardware, Lisbon, Portugal, August 31, 1998

1997
Design Issues and Tradeoffs for Write Buffers.
Proceedings of the 3rd IEEE Symposium on High-Performance Computer Architecture (HPCA '97), 1997

1996
Early Experience with Message-Passing on the SHRIMP Multicomputer.
Proceedings of the 23rd Annual International Symposium on Computer Architecture, 1996

1995
The performance impact of incomplete bypassing in processor pipelines.
Proceedings of the 28th Annual International Symposium on Microarchitecture, Ann Arbor, Michigan, USA, November 29, 1995

Evaluating Multi-Port Frame Buffer Designs for a Mesh-Connected Multicomputer.
Proceedings of the 22nd Annual International Symposium on Computer Architecture, 1995

1994
Maximal and Near-Maximal Shift Register Seqyences: Efficient Event Counters and Easy Discrete Logarithms.
IEEE Trans. Computers, 1994

Two virtual memory mapped network interface designs.
Proceedings of the Hot Interconnects II, 1994

1991
Performance From Architecture: Comparing a RISC and CISC with Similar Hardware Organization.
Proceedings of the ASPLOS-IV Proceedings, 1991

1988
Measuring VAX 8800 Performance with a Histogram Hardware Monitor.
Proceedings of the 15th Annual International Symposium on Computer Architecture, 1988

1987
Pipelining and Performance in the VAX 8800 Processor.
Proceedings of the Second International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS II), 1987

1985
Performance of the VAX-11/780 Translation Buffer: Simulation and Measurement
ACM Trans. Comput. Syst., 1985

1984
A Characterization of Processor Performance in the VAX-11/780.
Proceedings of the 11th Annual Symposium on Computer Architecture, 1984

1983
Cache Performance in the VAX-11/780
ACM Trans. Comput. Syst., 1983

1982
Measurement and analysis of instruction use in the VAX-11/780.
Proceedings of the 9th International Symposium on Computer Architecture (ISCA 1982), 1982

1981
The Memory System of a High-Performance Personal Computer.
IEEE Trans. Computers, 1981

1979
Measurements of Dynamic List Structure Use in Lisp.
IEEE Trans. Software Eng., 1979

Compact Encodings of List Structure.
ACM Trans. Program. Lang. Syst., 1979

1978
A Note on Shared List Structure in LISP.
Inf. Process. Lett., 1978

A Fast Algorithm for Copying List Structures.
Commun. ACM, 1978

1977
An Empirical Study of List Structure in Lisp.
Commun. ACM, 1977

1976
An Efficient List-Moving Algorithm Using Constant Workspace.
Commun. ACM, 1976

1975
A Fast Algorithm for Copying Binary Trees.
Inf. Process. Lett., 1975


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