Ding-Yong Hong

According to our database1, Ding-Yong Hong authored at least 26 papers between 2005 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Online presence:

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Bibliography

2021
Efficient Video Captioning on Heterogeneous System Architectures.
Proceedings of the 35th IEEE International Parallel and Distributed Processing Symposium, 2021

Accelerate CNN Models via Filter Pruning and Sparse Tensor Core.
Proceedings of the Ninth International Symposium on Computing and Networking, 2021

Optimal Branch Location for Cost-effective Inference on Branchynet.
Proceedings of the 2021 IEEE International Conference on Big Data (Big Data), 2021

2019
Exploiting SIMD Asymmetry in ARM-to-x86 Dynamic Binary Translation.
ACM Trans. Archit. Code Optim., 2019

Processor-Tracing Guided Region Formation in Dynamic Binary Translation.
ACM Trans. Archit. Code Optim., 2019

Optimizing data permutations in structured loads/stores translation and SIMD register mapping for a cross-ISA dynamic binary translator.
J. Syst. Archit., 2019

Exploiting Vector Processing in Dynamic Binary Translation.
Proceedings of the 48th International Conference on Parallel Processing, 2019

2018
Improving SIMD Parallelism via Dynamic Binary Translation.
ACM Trans. Embed. Comput. Syst., 2018

Efficient and retargetable SIMD translation in a dynamic binary translator.
Softw. Pract. Exp., 2018

Dynamic tuning of applications using restricted transactional memory.
Proceedings of the 2018 Conference on Research in Adaptive and Convergent Systems, 2018

Exploiting SIMD capability in an ARMv7-to-ARMv8 dynamic binary translator.
Proceedings of the International Conference on Compilers, 2018

2017
Dynamic translation of structured Loads/Stores and register mapping for architectures with SIMD extensions.
Proceedings of the 18th ACM SIGPLAN/SIGBED Conference on Languages, 2017

Exploiting Asymmetric SIMD Register Configurations in ARM-to-x86 Dynamic Binary Translation.
Proceedings of the 26th International Conference on Parallel Architectures and Compilation Techniques, 2017

2016
Optimizing Control Transfer and Memory Virtualization in Full System Emulators.
ACM Trans. Archit. Code Optim., 2016

Exploiting Longer SIMD Lanes in Dynamic Binary Translation.
Proceedings of the 22nd IEEE International Conference on Parallel and Distributed Systems, 2016

2015
A dynamic binary translation system in a client/server environment.
J. Syst. Archit., 2015

SIMD Code Translation in an Enhanced HQEMU.
Proceedings of the 21st IEEE International Conference on Parallel and Distributed Systems, 2015

2014
Efficient and Retargetable Dynamic Binary Translation on Multicores.
IEEE Trans. Parallel Distributed Syst., 2014

DBILL: an efficient and retargetable dynamic binary instrumentation framework using llvm backend.
Proceedings of the 10th ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments, 2014

2013
Improving dynamic binary optimization through early-exit guided code region formation.
Proceedings of the ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments (co-located with ASPLOS 2013), 2013

2012
HQEMU: a multi-threaded and retargetable dynamic binary translator on multicores.
Proceedings of the 10th Annual IEEE/ACM International Symposium on Code Generation and Optimization, 2012

2011
LnQ: Building High Performance Dynamic Binary Translators with Existing Compiler Backends.
Proceedings of the International Conference on Parallel Processing, 2011

2010
A Scalable HLA RTI System Based on Multiple-FedServ Architecture.
Proceedings of the 12th UKSim, 2010

2009
MGRID: a modifiable-grid region matching approach for DDM in the HLA RTI.
Proceedings of the 2009 Spring Simulation Multiconference, SpringSim 2009, 2009

2008
Early experiences in application level I/O tracing on blue gene systems.
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

2005
An Efficient MPI-IO for Noncontiguous Data Access over InfiniBand.
Proceedings of the 8th International Symposium on Parallel Architectures, 2005


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