Dong-Wan Ko

According to our database¹, Dong-Wan Ko authored at least 3 papers between 2021 and 2025.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of four.

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2025

A 16Gb 12.7Gb/s/pin LPDDR5-Ultra-Pro DRAM with 4-Phase Self-Calibration and AC-Coupled Transceiver Equalization in a 5<sup>th</sup>-Generation 10nm DRAM Process.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2025

2022

A Single-Ended Transmitter With Low Switching Noise Injection and Quadrature Clock Correction Schemes for DRAM Interface.

[BibT_eX]

[DOI]

Dong-Wan Ko

Won-Young Lee

IEEE Access, 2022

2021

A Low EMI Transmitter for DRAM Interface with Quadrature Clock Corrector.

[BibT_eX]

[DOI]

Dong-Wan Ko

Won-Young Lee

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Dong-Wan Ko

Timeline

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