Seung-Jun Bae

According to our database1, Seung-Jun Bae authored at least 46 papers between 2007 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2021
A Duo-Binary Transceiver With Time-Based Receiver and Voltage-Mode Time-Interleaved Mixing Transmitter for DRAM Interface.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

An 8.5-Gb/s/Pin 12-Gb LPDDR5 SDRAM With a Hybrid-Bank Architecture, Low Power, and Speed-Boosting Techniques.
IEEE J. Solid State Circuits, 2021

25.2 A 16Gb Sub-1V 7.14Gb/s/pin LPDDR5 SDRAM Applying a Mosaic Architecture with a Short-Feedback 1-Tap DFE, an FSS Bus with Low-Level Swing and an Adaptively Controlled Body Biasing in a 3<sup>rd</sup>-Generation 10nm DRAM.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

Session 16 Overview: Computation in Memory Memory Subcommittee.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

2020
A 7.5 Gb/s/pin 8-Gb LPDDR5 SDRAM With Various High-Speed and Low-Power Techniques.
IEEE J. Solid State Circuits, 2020

22.2 An 8.5Gb/s/pin 12Gb-LPDDR5 SDRAM with a Hybrid-Bank Architecture using Skew-Tolerant, Low-Power and Speed-Boosting Techniques in a 2nd generation 10nm DRAM Process.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2019
A 16-Gb, 18-Gb/s/pin GDDR6 DRAM With Per-Bit Trainable Single-Ended DFE and PLL-Less Clocking.
IEEE J. Solid State Circuits, 2019

Introduction to the Special Issue on the 2018 International Solid-State Circuits Conference (ISSCC).
IEEE J. Solid State Circuits, 2019

A 5Gb/s/pin 16Gb LPDDR4/4X Reconfigurable SDRAM with Voltage-High Keeper and a Prediction-based Fast-tracking ZQ Calibration.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

An 8-bit 2.8 GS/s Flash ADC with Time-based Offset Calibration and Interpolation in 65 nm CMOS.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019

2018
A Time-Based Receiver With 2-Tap Decision Feedback Equalizer for Single-Ended Mobile DRAM Interface.
IEEE J. Solid State Circuits, 2018

Dual-Loop Two-Step ZQ Calibration for Dynamic Voltage-Frequency Scaling in LPDDR4 SDRAM.
IEEE J. Solid State Circuits, 2018

A sub-0.85V, 6.4GBP/S/Pin TX-Interleaved Transceiver with Fast Wake-Up Time Using 2-Step Charging Control and VOHCalibration in 20NM DRAM Process.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018


Session 12 overview: DRAM: Memory subcommittee.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2017
Session 23 overview: DRAM, MRAM & DRAM interfaces.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

23.7 A time-based receiver with 2-tap DFE for a 12Gb/s/pin single-ended transceiver of mobile DRAM interface in 0.8V 65nm CMOS.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017



F5: Wireline transceivers for Mega Data Centers: 50Gb/s and beyond.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017


2016
A 40 mV-Differential-Channel-Swing Transceiver Using a RX Current-Integrating TIA and a TX Pre-Emphasis Equalizer With a CML Driver at 9 Gb/s.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

A low-EMI four-bit four-wire single-ended DRAM interface by using a three-level balanced coding scheme.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

18.1 A 20nm 9Gb/s/pin 8Gb GDDR5 DRAM with an NBTI monitor, jitter reduction techniques and improved power distribution.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

Crosstalk avoidance code for direct pass-through architecture.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015
A 9.6 Gb/s 0.96 mW/Gb/s Forwarded Clock Receiver With High Jitter Tolerance Using Mixing Cell Integrated Injection-Locked Oscillator.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

A 6.4Gb/s/pin at sub-1V supply voltage TX-interleaving technique for mobile DRAM interface.
Proceedings of the Symposium on VLSI Circuits, 2015

2014
A 40-mV-Swing Single-Ended Transceiver for TSV with a Switched-Diode RX Termination.
IEEE Trans. Circuits Syst. II Express Briefs, 2014

A Forwarded-Clock Receiver With Constant and Wide-Range Jitter-Tracking Bandwidth.
IEEE Trans. Circuits Syst. II Express Briefs, 2014

25.1 A 3.2Gb/s/pin 8Gb 1.0V LPDDR4 SDRAM with integrated ECC engine for sub-1V DRAM core operation.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2013
An 8Gb/s 0.65mW/Gb/s forwarded-clock receiver using an ILO with dual feedback loop and quadrature injection scheme.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2012
An 8GB/s quad-skew-cancelling parallel transceiver in 90nm CMOS for high-speed DRAM interface.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

An on-chip TSV emulation using metal bar surrounded by metal ring to develop interface circuits.
Proceedings of the International SoC Design Conference, 2012

2011
A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM With 2.5 ns Bank to Bank Active Time and No Bank Group Restriction.
IEEE J. Solid State Circuits, 2011

A Single-Loop SS-LMS Algorithm With Single-Ended Integrating DFE Receiver for Multi-Drop DRAM Interface.
IEEE J. Solid State Circuits, 2011

Performance of greedy policies for downlink scheduling in networks with relay stations.
IEICE Electron. Express, 2011


2010

A crosstalk-and-ISI equalizing receiver in 2-drop single-ended SSTL memory channel.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2009
A 2-Gb/s CMOS Integrating Two-Tap DFE Receiver for Four-Drop Single-Ended Signaling.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

A 0.13-µm CMOS 6 Gb/s/pin Memory Transceiver Using Pseudo-Differential Signaling for Removing Common-Mode Noise Due to SSN.
IEEE J. Solid State Circuits, 2009

A 6Gb/s/pin pseudo-differential signaling using common-mode noise rejection techniques without reference signal for DRAM interfaces.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2008
An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion.
IEEE J. Solid State Circuits, 2008

A 3.2Gb/s 8b Single-Ended Integrating DFE RX for 2-Drop DRAM Interface with Internal Reference Voltage and Digital Calibration.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

A 60nm 6Gb/s/pin GDDR5 Graphics DRAM with Multifaceted Clocking and ISI/SSN-Reduction Techniques.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2007


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