Daihyun Lim
According to our database1,
Daihyun Lim
authored at least 14 papers
between 2004 and 2024.
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Bibliography
2024
13.2 A 32Gb 8.0Gb/s/pin DDR5 SDRAM with a Symmetric-Mosaic Architecture in a 5<sup>th</sup>-Generation 10nm DRAM Process.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
A 1.01V 8.5Gb/s/pin 16Gb LPDDR5x SDRAM with Self-Pre-Emphasized Stacked-Tx, Supply Voltage Insensitive Rx, and Optimized Clock Using 4th-Generation 10nm DRAM Process for High-Speed and Low-Power Applications.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023
2020
A Dual-Polarization Silicon-Photonic Coherent Transmitter Supporting 552 Gb/s/wavelength.
IEEE J. Solid State Circuits, 2020
2019
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2019
A 6V Swing 3.6% THD >40GHz Driver with 4.5× Bandwidth Extension for a 272Gb/s Dual-Polarization 16-QAM Silicon Photonic Transmitter.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
2018
A Silicon Photonic Transceiver and Hybrid Tunable Laser for 64 Gbaud Coherent Communication.
Proceedings of the Optical Fiber Communications Conference and Exposition, 2018
2008
PhD thesis, 2008
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008
2007
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
A 70GHz Manufacturable Complementary LC-VCO with 6.14GHz Tuning Range in 65nm SOI CMOS.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
A Data-Driven Statistical Approach to Analyzing Process Variation in 65nm SOI Technology.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007
2005
IEEE Trans. Very Large Scale Integr. Syst., 2005
2004