Jin Yang

Orcid: 0000-0002-4372-926X

Affiliations:

Intel Corporation, Hillsboro, OR, USA

According to our database¹, Jin Yang authored at least 43 papers between 2000 and 2024.

Collaborative distances:

Dijkstra number² of three.
Erdős number³ of three.

Timeline

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PhD thesis

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Bibliography

2024

Correct-by-Construction Design of Custom Accelerator Microarchitectures.

[BibT_eX]

[DOI]

IEEE Trans. Computers, January, 2024

2023

Towards A Correct-by-Construction FHE Model.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2023

High-level Synthesis for Domain Specific Computing.

[BibT_eX]

[DOI]

Proceedings of the 2023 International Symposium on Physical Design, 2023

An Automated Verification Framework for HalideIR-Based Compiler Transformations.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Invited: A Scalable Formal Approach for Correctness-Assured Hardware Design.

[BibT_eX]

[DOI]

Jin Yang

Jeremy Casas

Zhenkun Yang

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

Towards A Formally Verified Fully Homomorphic Encryption Compute Engine.

[BibT_eX]

[DOI]

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

An Equivalence Checking Framework for Agile Hardware Design.

[BibT_eX]

[DOI]

Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2022

Mining Patterns From Concurrent Execution Traces.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Accelerator design with decoupled hardware customizations: benefits and challenges: invited.

[BibT_eX]

[DOI]

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021

A Hertzian contact based model to estimate thermal resistance of thermal interface material for high-performance microprocessors.

[BibT_eX]

[DOI]

David Shia

Jin Yang

Microelectron. J., 2021

A Highly Configurable Hardware/Software Stack for DNN Inference Acceleration.

[BibT_eX]

[DOI]

CoRR, 2021

Model Synthesis for Communication Traces of System-on-Chip Designs.

[BibT_eX]

[DOI]

CoRR, 2021

A Comparative Study of Specification Mining Methods for SoC Communication Traces.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021

Mining Message Flows from System-on-Chip Execution Traces.

[BibT_eX]

[DOI]

Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021

Model Synthesis for Communication Traces of System Designs.

[BibT_eX]

[DOI]

Proceedings of the 39th IEEE International Conference on Computer Design, 2021

2020

A Post-Silicon Trace Analysis Approach for System-on-Chip Protocol Debug.

[BibT_eX]

[DOI]

CoRR, 2020

Mining Message Flows using Recurrent Neural Networks for System-on-Chip Designs.

[BibT_eX]

[DOI]

Proceedings of the 21st International Symposium on Quality Electronic Design, 2020

UEFI Firmware Fuzzing with Simics Virtual Platform.

[BibT_eX]

[DOI]

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2017

A Post-Silicon Trace Analysis Approach for System-on-Chip Protocol Debug.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

2016

Protocol-guided analysis of post-silicon traces under limited observability.

[BibT_eX]

[DOI]

Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

2015

Correctness and security at odds: post-silicon validation of modern SoC designs.

[BibT_eX]

[DOI]

Proceedings of the 52nd Annual Design Automation Conference, 2015

2014

From visual to logical formalisms for SoC validation.

[BibT_eX]

[DOI]

Proceedings of the Twelfth ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2014

Security of SoC firmware load protocols.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE International Symposium on Hardware-Oriented Security and Trust, 2014

2012

Formal-Analysis-Based Trace Computation for Post-Silicon Debug.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2012

SystemVerilog Assertions: Past, Present, and Future SVA Standardization Experience.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2012

2010

Optimizing equivalence checking for behavioral synthesis.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

2009

Formal Verification for High-Assurance Behavioral Synthesis.

[BibT_eX]

[DOI]

Proceedings of the Automated Technology for Verification and Analysis, 2009

2008

BackSpace: Formal Analysis for Post-Silicon Debug.

[BibT_eX]

[DOI]

Proceedings of the Formal Methods in Computer-Aided Design, 2008

Optimizing automatic abstraction refinement for generalized symbolic trajectory evaluation.

[BibT_eX]

[DOI]

Yan Chen

Fei Xie

Jin Yang

Proceedings of the 45th Design Automation Conference, 2008

2007

Automatic Abstraction Refinement for Generalized Symbolic Trajectory Evaluation.

[BibT_eX]

[DOI]

Proceedings of the Formal Methods in Computer-Aided Design, 7th International Conference, 2007

2006

Optimal synthesis of multiple output Boolean functions using a set of quantum gates by symbolic reachability analysis.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Maximal Models of Assertion Graph in GSTE.

[BibT_eX]

[DOI]

Proceedings of the Theory and Applications of Models of Computation, 2006

Verification Challenges and Opportunities in the New Era of Microprocessor Design.

[BibT_eX]

[DOI]

Jin Yang

Proceedings of the Automated Technology for Verification and Analysis, 2006

2005

Implication of assertion graphs in GSTE.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Tightly integrate dynamic verification with formal verification: a GSTE based approach.

[BibT_eX]

[DOI]

Jin Yang

Avi Puder

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Partitioned model checking from software specifications.

[BibT_eX]

[DOI]

Xiushan Feng

Alan J. Hu

Jin Yang

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

Quantum logic synthesis by symbolic reachability analysis.

[BibT_eX]

[DOI]

Proceedings of the 41th Design Automation Conference, 2004

Compositional Specification and Model Checking in GSTE.

[BibT_eX]

[DOI]

Jin Yang

Carl-Johan H. Seger

Proceedings of the Computer Aided Verification, 16th International Conference, 2004

2003

Introduction to generalized symbolic trajectory evaluation.

[BibT_eX]

[DOI]

Jin Yang

Carl-Johan H. Seger

IEEE Trans. Very Large Scale Integr. Syst., 2003

Reasoning about GSTE Assertion Graphs.

[BibT_eX]

[DOI]

Alan J. Hu

Jeremy Casas

Jin Yang

Proceedings of the Correct Hardware Design and Verification Methods, 2003

2002

GSTE through a case study.

[BibT_eX]

[DOI]

Jin Yang

Amit Goel

Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

Generalized Symbolic Trajectory Evaluation - Abstraction in Action.

[BibT_eX]

[DOI]

Jin Yang

Carl-Johan H. Seger

Proceedings of the Formal Methods in Computer-Aided Design, 4th International Conference, 2002

2000

Lazy symbolic model checking.

[BibT_eX]

[DOI]

Jin Yang

Andreas Tiemeyer

Proceedings of the 37th Conference on Design Automation, 2000

Jin Yang

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