Doug C. H. Yu

According to our database, Doug C. H. Yu authored at least 6 papers between 2014 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2024

A 28-nm 141.4TOPS/W Scalable Reconfigurable Deep Learning SoC for Large-Scale Neural Networks.

I-Hsuan Liu, I-Ting Lin, Yueh-Feng Tsai, Jeng-Sheng Hsieh, Vincent Chen, Chuei-Tang Wang, Chia-Hsiang Yang, Douglas C. H. Yu

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2024

2023

An Integrated System Scaling Solution for Future High Performance Computing.

Chih-Hang Tung, Doug C. H. Yu

Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

2022

SoIC_H Technology for Heterogenous System Integration.

Chuei-Tang Wang, Chia-Chai Lin, Chih-Hsin Lu, Wei-Ting Chen, Chung-Hao Tsai, Douglas C. H. Yu

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

2021

Ultra High Power Cooling Solution for 3D-ICs.

C. J. Wu, S. T. Hsiao, J. Y. Wang, W. H. Lin, C. W. Chang, T. L. Shao, C. H. Tung, Doug C. H. Yu

Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021

2015

Power saving and noise reduction of 28nm CMOS RF system integration using integrated fan-out wafer level packaging (InFO-WLP) technology.

Chuei-Tang Wang, Jeng-Shien Hsieh, Victor C. Y. Chang, En-Hsiang Yeh, Feng-Wei Kuo, Hsu-Hsien Chen, Chih-Hua Chen, Huan-Neng Ron Chen, Ying-Ta Lu, Chewnpu Jou, Hao-Yi Tsai, C. S. Liu, Doug C. H. Yu

Proceedings of the 2015 International 3D Systems Integration Conference, 2015

2014

New System-in-Package (SiP) Integration technologies.

Doug C. H. Yu

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014