Feng-Wei Kuo

According to our database1, Feng-Wei Kuo authored at least 10 papers between 2014 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.



In proceedings 
PhD thesis 


On csauthors.net:


A 0.85mm<sup>2</sup> 51%-Efficient 11-dBm Compact DCO-DPA in 16-nm FinFET for Sub-Gigahertz IoT TX Using HD<sub>2</sub> Self-Suppression and Pulling Mitigation.
IEEE J. Solid State Circuits, 2019

A 77/79-GHz Frequency Generator in 16-nm CMOS for FMCW Radar Applications Based on a 26-GHz Oscillator with Co-Generated Third Harmonic.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019

An All-Digital PLL for Cellular Mobile Phones in 28-nm CMOS with -55 dBc Fractional and -91 dBc Reference Spurs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

A 0.5-V 1.6-mW 2.4-GHz Fractional-N All-Digital PLL for Bluetooth LE With PVT-Insensitive TDC Using Switched-Capacitor Doubler in 28-nm CMOS.
IEEE J. Solid State Circuits, 2018

A Bluetooth Low-Energy Transceiver With 3.7-mW All-Digital Transmitter, 2.75-mW High-IF Discrete-Time Receiver, and TX/RX Switchable On-Chip Matching Network.
IEEE J. Solid State Circuits, 2017

A Fully Integrated Bluetooth Low-Energy Transmitter in 28 nm CMOS With 36% System Efficiency at 3 dBm.
IEEE J. Solid State Circuits, 2016

A Bluetooth low-energy (BLE) transceiver with TX/RX switchable on-chip matching network, 2.75mW high-IF discrete-time receiver, and 3.6mW all-digital transmitter.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

A fully integrated 28nm Bluetooth Low-Energy transmitter with 36% system efficiency at 3dBm.
Proceedings of the ESSCIRC Conference 2015, 2015

Power saving and noise reduction of 28nm CMOS RF system integration using integrated fan-out wafer level packaging (InFO-WLP) technology.
Proceedings of the 2015 International 3D Systems Integration Conference, 2015

A 12mW all-digital PLL based on class-F DCO for 4G phones in 28nm CMOS.
Proceedings of the Symposium on VLSI Circuits, 2014