Chia-Hsiang Yang
Orcid: 0000-0003-1163-321X
According to our database1,
Chia-Hsiang Yang
authored at least 90 papers
between 2004 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
2.6 A 131mW 6.4Gbps 256×32 Multi-User MIMO OTFS Detector for Next-Gen Communication Systems.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
30.4 A Fully Integrated Annealing Processor for Large-Scale Autonomous Navigation Optimization.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
An FM-Index Based High-Throughput Memory-Efficient FPGA Accelerator for Paired-End Short-Read Mapping.
IEEE Trans. Biomed. Circuits Syst., December, 2023
IEEE J. Solid State Circuits, February, 2023
An Energy-Efficient Double Ratchet Cryptographic Processor With Backward Secrecy for IoT Devices.
IEEE J. Solid State Circuits, 2023
A 96.2-nJ/class Neural Signal Processor With Adaptable Intelligence for Seizure Prediction.
IEEE J. Solid State Circuits, 2023
A 169mW Fully-Integrated Ultrasound Imaging Processor Supporting Advanced Modes for Hand-Held Devices.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
A 28nm 11.2TOPS/W Hardware-Utilization-Aware Neural-Network Accelerator with Dynamic Dataflow.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
A Fully Integrated End-to-End Genome Analysis Accelerator for Next-Generation Sequencing.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023
2022
Achieving Accurate Automatic Sleep Apnea/Hypopnea Syndrome Assessment Using Nasal Pressure Signal.
IEEE J. Biomed. Health Informatics, 2022
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
A 28-nm 25.1 TOPS/W Sparsity-Aware CNN-GCN Deep Learning SoC for Mobile Augmented Reality.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
Hardware Acceleration in Large-Scale Tensor Decomposition for Neural Network Compression.
Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, 2022
A 96.2nJ/class Neural Signal Processor with Adaptable Intelligence for Seizure Prediction.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
2021
IEEE Trans. Parallel Distributed Syst., 2021
A 975-mW Fully Integrated Genetic Variant Discovery System-on-Chip in 28 nm for Next-Generation Sequencing.
IEEE J. Solid State Circuits, 2021
Design of a Bone-Guided Cochlear Implant Microsystem With Monopolar Biphasic Multiple Stimulations and Evoked Compound Action Potential Acquisition and Its In Vivo Verification.
IEEE J. Solid State Circuits, 2021
A 1.5-μJ/Task Path-Planning Processor for 2-D/3-D Autonomous Navigation of Microrobots.
IEEE J. Solid State Circuits, 2021
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
A Color Doppler Processing Engine with an Adaptive Clutter Filter for Portable Ultrasound Imaging Devices.
Proceedings of the IEEE International Conference on Acoustics, 2021
A 1.18mW Double Ratchet Cryptographic Processor with Backward Secrecy for IoT Devices.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021
2020
A 1.5 mW Programmable Acoustic Signal Processor for Hearing Assistive Devices With Speech Intelligibility Enhancement.
IEEE Trans. Circuits Syst., 2020
A 2.17-mW Acoustic DSP Processor With CNN-FFT Accelerators for Intelligent Hearing Assistive Devices.
IEEE J. Solid State Circuits, 2020
IEEE J. Solid State Circuits, 2020
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
Proceedings of the 2020 International Symposium on VLSI Design, Automation and Test, 2020
Proceedings of the 2020 International Symposium on VLSI Design, Automation and Test, 2020
21.1 A Fully Integrated Genetic Variant Discovery SoC for Next-Generation Sequencing.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
21.2 A 1.5μJ/Task Path-Planning Processor for 2D/3D Autonomous Navigation of Micro Robots.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Proceedings of the IEEE Global Communications Conference, 2020
Improved Design and In Vivo Animal Tests of Bone-Guided Cochlear Implant Microsystem with Monopolar Biphasic Multiple Stimulation and Neural Action Potential Acquisition.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2020
2019
IEEE Trans. Signal Process., 2019
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
An Integrated Message-Passing Detector and Decoder for Polar-Coded Massive MU-MIMO Systems.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
IEEE Trans. Biomed. Eng., 2019
A 12.6 mW, 573-2901 kS/s Reconfigurable Processor for Reconstruction of Compressively Sensed Physiological Signals.
IEEE J. Solid State Circuits, 2019
CoRR, 2019
Proceedings of the International Symposium on VLSI Design, Automation and Test, 2019
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019
A 2.17mW Acoustic DSP Processor with CNN-FFT Accelerators for Intelligent Hearing Aided Devices.
Proceedings of the IEEE International Conference on Artificial Intelligence Circuits and Systems, 2019
2018
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
IEEE Trans. Circuits Syst. II Express Briefs, 2018
Introduction to the Special Section on the 2017 Asian Solid-State Circuits Conference (A-SSCC).
IEEE J. Solid State Circuits, 2018
A 12.6MW 573-2, 901KS/S Reconfigurable Processor for Reconstruction of Compressively-Sensed Phvsiological Signals.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
Proceedings of the 2018 International Symposium on VLSI Design, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
2017
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
IEEE Trans. Biomed. Circuits Syst., 2017
A 5.28-Gb/s LDPC Decoder With Time-Domain Signal Processing for IEEE 802.15.3c Applications.
IEEE J. Solid State Circuits, 2017
Proceedings of the 85th IEEE Vehicular Technology Conference, 2017
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
Integration of energy-recycling logic and wireless power transfer for ultra-low-power implantables.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
2016
A Standard-Cell-Design-Flow Compatible Energy-Recycling Logic With 70% Energy Saving.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
sBWT: memory efficient implementation of the hardware-acceleration-friendly Schindler transform for the fast biological sequence mapping.
Bioinform., 2016
Error-resilient sequential cells with successive time borrowing for stochastic computing.
Proceedings of the 2016 IEEE International Conference on Acoustics, 2016
Design of a 0.5 V 1.68mW nose-on-a-chip for rapid screen of chronic obstructive pulmonary disease.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2016
2015
IEEE Trans. Wirel. Commun., 2015
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
IEEE Trans. Biomed. Circuits Syst., 2015
A 794Mbps 135mW iterative detection and decoding receiver for 4×4 LDPC-coded MIMO systems in 40nm.
Proceedings of the Symposium on VLSI Circuits, 2015
2014
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
A Fully Parallel LDPC Decoder Architecture Using Probabilistic Min-Sum Algorithm for High-Throughput Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
A Fully Integrated Nose-on-a-Chip for Rapid Diagnosis of Ventilator-Associated Pneumonia.
IEEE Trans. Biomed. Circuits Syst., 2014
A Fully Integrated 8-Channel Closed-Loop Neural-Prosthetic CMOS SoC for Real-Time Epileptic Seizure Control.
IEEE J. Solid State Circuits, 2014
24.5 A 0.5V 1.27mW nose-on-a-chip for rapid diagnosis of ventilator-associated pneumonia.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
2013
CoRR, 2013
Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013
A fully integrated 8-channel closed-loop neural-prosthetic SoC for real-time epileptic seizure control.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013
2012
A 7.4-mW 200-MS/s Wideband Spectrum Sensing Digital Baseband Processor for Cognitive Radios.
IEEE J. Solid State Circuits, 2012
IEEE J. Solid State Circuits, 2012
Hardware-efficient EVD processor architecture in FastICA for epileptic seizure detection.
Proceedings of the Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, 2012
2011
Proceedings of the Global Communications Conference, 2011
Proceedings of the Global Communications Conference, 2011
2009
IEEE Trans. Circuits Syst. I Regul. Pap., 2009
Proceedings of the 35th European Solid-State Circuits Conference, 2009
2008
A Flexible VLSI Architecture for Extracting Diversity and Spatial Multiplexing Gains in MIMO Channels.
Proceedings of IEEE International Conference on Communications, 2008
Proceedings of the Global Communications Conference, 2008. GLOBECOM 2008, New Orleans, LA, USA, 30 November, 2008
2004
Design of a low-complexity receiver for impulse-radio ultra-wideband communication systems.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004