Dusan Stepanovic

According to our database, Dusan Stepanovic authored at least 4 papers between 2007 and 2017.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2017

16.5 An 8GS/s time-interleaved SAR ADC with unresolved decision detection achieving -58dBFS noise and 4GHz bandwidth in 28nm CMOS.

John P. Keane, Nathaniel J. Guilar, Dusan Stepanovic, Bernd Wuppermann, Charles Wu, Cheongyuen W. Tsang, Robert Neff, Ken Nishimura

Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2013

A 2.8 GS/s 44.6 mW Time-Interleaved ADC Achieving 50.9 dB SNDR and 3 dB Effective Resolution Bandwidth of 1.5 GHz in 65 nm CMOS.

Dusan Stepanovic, Borivoje Nikolic

IEEE J. Solid State Circuits, 2013

2012

A 2.8GS/s 44.6mW time-interleaved ADC achieving 50.9dB SNDR and 3dB effective resolution bandwidth of 1.5GHz in 65nm CMOS.

Dusan Stepanovic, Borivoje Nikolic

Proceedings of the Symposium on VLSI Circuits, 2012

2007

Improving network security using genetic algorithm approach.

Zorana Bankovic, Dusan Stepanovic, Slobodan Bojanic, Octavio Nieto-Taladriz

Comput. Electr. Eng., 2007