Borivoje Nikolic

Parthasarathy Ranganathan

Mototsugu Hamada

IEEE J. Solid State Circuits, 2023

AuRORA: Virtualized Accelerator Orchestration for Multi-Tenant Workloads.

[BibT_eX]

[DOI]

Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023

RoSÉ: A Hardware-Software Co-Simulation Infrastructure Enabling Pre-Silicon Full-Stack Robotics SoC Evaluation.

[BibT_eX]

[DOI]

Proceedings of the 50th Annual International Symposium on Computer Architecture, 2023

CDPU: Co-designing Compression and Decompression Processing Units for Hyperscale Systems.

[BibT_eX]

[DOI]

Proceedings of the 50th Annual International Symposium on Computer Architecture, 2023

MoCA: Memory-Centric, Adaptive Execution for Multi-Tenant Deep Neural Networks.

[BibT_eX]

[DOI]

Seah Kim

Hasan Genc

Vadim Vadimovich Nikiforov

Krste Asanovic

Alexandra Gallyas-Sanhueza

Yakun Sophia Shao

Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023

A Heterogeneous SoC for Bluetooth LE in 28nm.

[BibT_eX]

[DOI]

Proceedings of the 35th IEEE Hot Chips Symposium, 2023

Silicon Process Technology Constraints for Standardized Vertical Die-to-Die Interconnects.

[BibT_eX]

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2023

Simulator Independent Coverage for RTL Hardware Languages.

[BibT_eX]

[DOI]

Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2023

2022

An Adaptable and Scalable Generator of Distributed Massive MIMO Baseband Processing Systems.

[BibT_eX]

[DOI]

Yue Dai

Maryam Eslami Rasekh

Seyed Hadi Mirfarshbafan

Harrison Liew

J. Signal Process. Syst., 2022

Automated Design of Analog Circuits Using Reinforcement Learning.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

An Eight-Core 1.44-GHz RISC-V Vector Processor in 16-nm FinFET.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2022

Design Techniques for a 6.4-32-Gb/s 0.96-pJ/b Continuous-Rate CDR With Stochastic Frequency-Phase Detector.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2022

Guest Editorial Introduction to the Special Issue on the 2021 Symposium on VLSI Circuits.

[BibT_eX]

[DOI]

Yusuke Oike

IEEE J. Solid State Circuits, 2022

ML for Analog Design: Good Progress, but More to Do.

[BibT_eX]

[DOI]

Alexandra Gallyas-Sanhueza

Proceedings of the 2022 ACM/IEEE Workshop on Machine Learning for CAD, 2022

Hammer: a modular and reusable physical design flow tool: invited.

[BibT_eX]

[DOI]

Nayiri Krzysztofowicz

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021

LAYGO: A Template-and-Grid-Based Layout Generation Engine for Advanced CMOS Technologies.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Accessible, FPGA Resource-Optimized Simulation of Multiclock Systems in FireSim.

[BibT_eX]

[DOI]

IEEE Micro, 2021

A 71-to-86-GHz 16-Element by 16-Beam Multi-User Beamforming Integrated Receiver Sub-Array for Massive MIMO.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2021

Improved Processor Design Project Testing.

[BibT_eX]

[DOI]

Proceedings of the ACM/IEEE Workshop on Computer Architecture Education, 2021

A Scalable Generator for Massive MIMO Baseband Processing Systems with Beamspace Channel Estimation.

[BibT_eX]

[DOI]

Yue Dai

Harrison Liew

Maryam Eslami Rasekh

Seyed Hadi Mirfarshbafan

Proceedings of the IEEE Workshop on Signal Processing Systems, 2021

A Hardware Accelerator for Protocol Buffers.

[BibT_eX]

[DOI]

Parthasarathy Ranganathan

Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021

4.3 An Eight-Core 1.44GHz RISC-V Vector Machine in 16nm FinFET.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2021

14.1 A 71-to-86GHz Packaged 16-Element by 16-Beam Multi-User Beamforming Integrated Receiver in 28nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2021

Memory-Efficient Hardware Performance Counters with Approximate-Counting Algorithms.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2021

Vertically Integrated Computing Labs Using Open-Source Hardware Generators and Cloud-Hosted FPGAs.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

A Scalable Massive MIMO Uplink Baseband Processing Generator.

[BibT_eX]

[DOI]

Proceedings of the ICC 2021, 2021

A 16mm2 106.1 GOPS/W Heterogeneous RISC-V Multi-Core Multi-Accelerator SoC in Low-Power 22nm FinFET.

[BibT_eX]

[DOI]

Proceedings of the 47th ESSCIRC 2021, 2021

An Automated and Process-Portable Generator for Phase-Locked Loop.

[BibT_eX]

[DOI]

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

Gemmini: Enabling Systematic Deep-Learning Architecture Evaluation via Full-Stack Integration.

[BibT_eX]

[DOI]

Jonathan Ragan-Kelley

Krste Asanovic

Yakun Sophia Shao

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020

A Dual-Core RISC-V Vector Processor With On-Chip Fine-Grain Power Management in 28-nm FD-SOI.

[BibT_eX]

[DOI]

John Charles Wright

Colin Schmidt

Ben Keller

IEEE Trans. Very Large Scale Integr. Syst., 2020

Chipyard: Integrated Design, Simulation, and Implementation Framework for Custom SoCs.

[BibT_eX]

[DOI]

IEEE Micro, 2020

Wireless Channel Dynamics for Relay Selection under Ultra-Reliable Low-Latency Communication.

[BibT_eX]

[DOI]

Paul Rigge

Proceedings of the 31st IEEE Annual International Symposium on Personal, 2020

A Methodology for Reusable Physical Design.

[BibT_eX]

[DOI]

Proceedings of the 21st International Symposium on Quality Electronic Design, 2020

Design and Demonstration of a Scalable Massive MIMO Uplink at E-Band.

[BibT_eX]

[DOI]

Proceedings of the 2020 IEEE International Conference on Communications Workshops, 2020

AutoCkt: Deep Reinforcement Learning of Analog Circuit Designs.

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Invited: Chipyard - An Integrated SoC Research and Implementation Environment.

[BibT_eX]

[DOI]

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

FirePerf: FPGA-Accelerated Full-System Hardware/Software Performance Profiling and Co-Design.

[BibT_eX]

[DOI]

Proceedings of the ASPLOS '20: Architectural Support for Programming Languages and Operating Systems, 2020

2019

FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud.

[BibT_eX]

[DOI]

IEEE Micro, 2019

BROOM: An Open-Source Out-of-Order Processor With Resilient Low-Voltage Operation in 28-nm CMOS.

[BibT_eX]

[DOI]

IEEE Micro, 2019

A Real-Time, 1.89-GHz Bandwidth, 175-kHz Resolution Sparse Spectral Analysis RISC-V SoC in 16-nm FinFET.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2019

A Mixed-Signal RISC-V Signal Analysis SoC Generator With a 16-nm FinFET Instance.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2019

Wireless Channel Dynamics and Robustness for Ultra-Reliable Low-Latency Communications.

[BibT_eX]

[DOI]

IEEE J. Sel. Areas Commun., 2019

Gemmini: An Agile Systolic Array Generator Enabling Systematic Evaluations of Deep-Learning Architectures.

[BibT_eX]

[DOI]

CoRR, 2019

RTL bug localization through LTL specification mining (WIP).

[BibT_eX]

[DOI]

Proceedings of the 17th ACM-IEEE International Conference on Formal Methods and Models for System Design, 2019

Open-Source EDA Tools and IP, A View from the Trenches.

[BibT_eX]

[DOI]

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

A Generated 7GS/s 8b Time-Interleaved SAR ADC with 38.2dB SNDR at Nyquist in 16nm CMOS FinFET.

[BibT_eX]

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

A 3.01 mm2 65.38Gb/s Stochastic LDPC Decoder for IEEE 802.3an in 65 nm.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019

2018

A Variation-Tolerant, Sneak-Current-Compensated Readout Scheme for Cross-Point Memory Based on Two-Port Sensing Technique.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2018

A 65-nm CMOS I/Q RF Power DAC With 24- to 42-dB Third-Harmonic Cancellation and Up to 18-dB Mixed-Signal Filtering.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2018

Network Coding for Real-time Wireless Communication for Automation.

[BibT_eX]

[DOI]

CoRR, 2018

A Dual-Mode Configurable RF-to-Digital Receiver in 16NM FinFET.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

An Out-of-Order RISC-V Processor with Resilient Low-Voltage Operation in 28NM CMOS.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

Predicting Wireless Channels for Ultra-Reliable Low-Latency Communications.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE International Symposium on Information Theory, 2018

Energy-Efficient Design in FDSOI.

[BibT_eX]

[DOI]

Proceedings of the 48th European Solid-State Device Research Conference, 2018

A Real-Time, Analog/Digital Co-Designed 1.89-GHz Bandwidth, 175-kHz Resolution Sparse Spectral Analysis RISC-V SoC in 16-nm FinFET.

[BibT_eX]

[DOI]

Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018

Generating the Next Wave of Custom Silicon.

[BibT_eX]

[DOI]

Elad Alon

Krste Asanovic

Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018

ACED: a hardware library for generating DSP systems.

[BibT_eX]

[DOI]

Proceedings of the 55th Annual Design Automation Conference, 2018

BAG2: A process-portable framework for generator-based AMS circuit design.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018

A 28nm FDSOI 8192-point digital ASIC spectrometer from a Chisel generator.

[BibT_eX]

[DOI]

Dan Werthimer

Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018

A Generated Multirate Signal Analysis RISC-V SoC in 16nm FinFET.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

2017

Real-Time Cooperative Communication for Automation Over Wireless.

[BibT_eX]

[DOI]

IEEE Trans. Wirel. Commun., 2017

Use of Phase Delay Analysis for Evaluating Wideband Circuits: An Alternative to Group Delay Analysis.

[BibT_eX]

[DOI]

Woo-Rham Bae

Deog-Kyoon Jeong

IEEE Trans. Very Large Scale Integr. Syst., 2017

Reprogrammable Redundancy for SRAM-Based Cache Vmin Reduction in a 28-nm RISC-V Processor.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2017

A 65-nm CMOS Wideband TDD Front-End With Integrated T/R Switching via PA Re-Use.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2017

A RISC-V Processor SoC With Integrated Power Management at Submicrosecond Timescales in 28 nm FD-SOI.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2017

Analysis and Design of Integrated Active Cancellation Transceiver for Frequency Division Duplex Systems.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2017

A yield optimization methodology for mixed-signal circuits.

[BibT_eX]

[DOI]

Aikaterini Papadopoulou

Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

A 0.37mm2 LTE/Wi-Fi compatible, memory-based, runtime-reconfigurable 2n3m5k FFT accelerator integrated with a RISC-V core in 16nm FinFET.

[BibT_eX]

[DOI]

Angie Wang

Brian C. Richards

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017

A low-voltage low-offset dual strong-arm latch comparator.

[BibT_eX]

[DOI]

Aikaterini Papadopoulou

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017

On-chip spur and phase noise cancellation techniques.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017

2016

Design of Energy- and Cost-Efficient Massive MIMO Arrays.

[BibT_eX]

[DOI]

Antonio Puglielli

Andrew Townley

Greg LaCaille

Pengpeng Lu

Konstantin Trotskovsky

Proc. IEEE, 2016

A RISC-V Vector Processor With Simultaneous-Switching Switched-Capacitor DC-DC Converters in 28 nm FDSOI.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2016

A Self-Adjustable Clock Generator With Wide Dynamic Range in 28 nm FDSOI.

[BibT_eX]

[DOI]

Jaehwa Kwak

IEEE J. Solid State Circuits, 2016

Cooperative Communication for Control over Wireless.

[BibT_eX]

[DOI]

CoRR, 2016

Network coding for high-reliability low-latency wireless control.

[BibT_eX]

[DOI]

Proceedings of the IEEE Wireless Communications and Networking Conference Workshops, 2016

A 65nm CMOS transceiver with integrated active cancellation supporting FDD from 1GHz to 1.8GHz at +12.6dBm TX power leakage.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

A fast, flexible, positive and negative adaptive body-bias generator in 28nm FDSOI.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

Phase noise scaling and tracking in OFDM multi-user beamforming arrays.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Conference on Communications, 2016

A generator of memory-based, runtime-reconfigurable 2N3M5K FFT engines.

[BibT_eX]

[DOI]

Angie Wang

Jonathan Bachrach

Proceedings of the 2016 IEEE International Conference on Acoustics, 2016

On-chip I-V variability and random telegraph noise characterization in 28 nm CMOS.

[BibT_eX]

[DOI]

Amy Whitcombe

Scott Taylor

Martin Denham

Proceedings of the 46th European Solid-State Device Research Conference, 2016

A 65nm CMOS wideband TDD front-end with integrated T/R switching via PA re-use.

[BibT_eX]

[DOI]

Proceedings of the ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, 2016

Sub-microsecond adaptive voltage scaling in a 28nm FD-SOI processor SoC.

[BibT_eX]

[DOI]

Proceedings of the ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, 2016

Reprogrammable redundancy for cache Vmin reduction in a 28nm RISC-V processor.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

On-chip supply power measurement and waveform reconstruction in a 28nm FD-SOI processor SoC.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

A double-tail sense amplifier for low-voltage SRAM in 28nm technology.

[BibT_eX]

[DOI]

Pi-Feng Chiu

Brian Zimmer

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2015

Per-Core DVFS With Switched-Capacitor Converters for Energy Efficiency in Manycore Processors.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

A Differential 2R Crosspoint RRAM Array With Zero Standby Current.

[BibT_eX]

[DOI]

Pi-Feng Chiu

IEEE Trans. Circuits Syst. II Express Briefs, 2015

A RISC-V vector processor with tightly-integrated switched-capacitor DC-DC converters in 28nm FDSOI.

[BibT_eX]

[DOI]

Proceedings of the Symposium on VLSI Circuits, 2015

Design considerations for low-noise transconductance amplifiers in 28nm UTBB-FDSOI.

[BibT_eX]

[DOI]

Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

F1: High-speed interleaved ADCs.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

Cooperative communication for high-reliability low-latency wireless control.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Conference on Communications, 2015

A scalable massive MIMO array architecture based on common modules.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Communication, 2015

Raven: A 28nm RISC-V vector processor with integrated switched-capacitor DC-DC converters and adaptive clocking.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE Hot Chips 27 Symposium (HCS), 2015

Simpler, more efficient design.

[BibT_eX]

[DOI]

Proceedings of the ESSCIRC Conference 2015, 2015

A 550-2260MHz self-adjustable clock generator in 28nm FDSOI.

[BibT_eX]

[DOI]

Jaehwa Kwak

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015

2014

A Wideband 400 MHz-to-4 GHz Direct RF-to-Digital Multimode ΔΣ Receiver.

[BibT_eX]

[DOI]

Charles Wu

Elad Alon

IEEE J. Solid State Circuits, 2014

27.7 A scalable 1.5-to-6Gb/s 6.2-to-38.1mW LDPC decoder for 60GHz wireless networks in 28nm UTBB FDSOI.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

Design of a low-latency, high-reliability wireless communication system for control applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Communications, 2014

Joint impact of random variations and RTN on dynamic writeability in 28nm bulk and FDSOI SRAM.

[BibT_eX]

[DOI]

Proceedings of the 44th European Solid State Device Research Conference, 2014

A frequency-reconfigurable multi-standard 65nm CMOS digital transmitter with LTCC interposers.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014

2013

A 2.8 GS/s 44.6 mW Time-Interleaved ADC Achieving 50.9 dB SNDR and 3 dB Effective Resolution Bandwidth of 1.5 GHz in 65 nm CMOS.

[BibT_eX]

[DOI]

Dusan Stepanovic

IEEE J. Solid State Circuits, 2013

Coding and System Design for Quantize-Map-and-Forward Relaying.

[BibT_eX]

[DOI]

IEEE J. Sel. Areas Commun., 2013

Relay scheduling and interference cancellation for quantize-map-and-forward cooperative relaying.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Information Theory, 2013

A 0.4 GHz - 4 GHz direct RF-to-digital ΣΔ multi-mode receiver.

[BibT_eX]

[DOI]

Charles Wu

Proceedings of the ESSCIRC 2013, 2013

2012

A 15 MHz to 600 MHz, 20 mW, 0.38 mm2 Split-Control, Fast Coarse Locking Digital DLL in 0.13 µ m CMOS.

[BibT_eX]

[DOI]

Sebastian Hoyos

Cheongyuen W. Tsang

Johan P. Vanderhaegen

IEEE Trans. Very Large Scale Integr. Syst., 2012

SRAM Assist Techniques for Operation in a Wide Voltage Range in 28-nm CMOS.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2012

A 2.8GS/s 44.6mW time-interleaved ADC achieving 50.9dB SNDR and 3dB effective resolution bandwidth of 1.5GHz in 65nm CMOS.

[BibT_eX]

[DOI]

Dusan Stepanovic

Proceedings of the Symposium on VLSI Circuits, 2012

2011

Discrete-Time, Linear Periodically Time-Variant Phase-Locked Loop Model for Jitter Analysis.

[BibT_eX]

[DOI]

Socrates D. Vamvakos

Vladimir Stojanovic

IEEE Trans. Circuits Syst. I Regul. Pap., 2011

Technology Variability From a Design Perspective.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2011

Characterization of Dynamic SRAM Stability in 45 nm CMOS.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2011

A 2 Gb/s 5.6 mW Digital LOS/NLOS Equalizer for the 60 GHz Band.

[BibT_eX]

[DOI]

Ji-Hoon Park

Brian C. Richards

IEEE J. Solid State Circuits, 2011

LDPC decoder architecture for high-data rate personal-area networks.

[BibT_eX]

[DOI]

Matthew Weiner

Zhengya Zhang

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Managing variability for ultimate energy efficiency.

[BibT_eX]

[DOI]

Proceedings of the 20th European Conference on Circuit Theory and Design, 2011

2010

SRAM Read/Write Margin Enhancements Using FinFETs.

[BibT_eX]

[DOI]

Andrew Carlson

Zheng Guo

Sriram Balasubramanian

Tsu-Jae King Liu

IEEE Trans. Very Large Scale Integr. Syst., 2010

Analysis of absorbing sets and fully absorbing sets of array-based LDPC codes.

[BibT_eX]

[DOI]

IEEE Trans. Inf. Theory, 2010

An Efficient 10GBASE-T Ethernet LDPC Decoder Design With Low Error Floors.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2010

SRAM stability characterization using tunable ring oscillators in 45nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

SRAM design in fully-depleted SOI technology.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Parameter-specific ring oscillator for process monitoring at the 45 nm node.

[BibT_eX]

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

Technology variability from a design perspective.

[BibT_eX]

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

Quantize-map-and-forward relaying: Coding and system design.

[BibT_eX]

[DOI]

Proceedings of the 48th Annual Allerton Conference on Communication, 2010

2009

Design of LDPC decoders for improved low error rate performance: quantization and algorithm choices.

[BibT_eX]

[DOI]

IEEE Trans. Commun., 2009

Energy-Delay Optimization of 64-Bit Carry-Lookahead Adders With a 240 ps 90 nm CMOS Design Example.

[BibT_eX]

[DOI]

Sean Kao

IEEE J. Solid State Circuits, 2009

Measurement and Analysis of Variability in 45 nm Strained-Si CMOS Technology.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2009

Measurements and Analysis of Process Variability in 90nmCMOS.

[BibT_eX]

[DOI]

Liang-Teck Pang

IEEE J. Solid State Circuits, 2009

Large-Scale SRAM Variability Characterization in 45 nm CMOS.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2009

Predicting error floors of structured LDPC codes: deterministic bounds and estimates.

[BibT_eX]

[DOI]

IEEE J. Sel. Areas Commun., 2009

Cooperative multiplexing in the multiple antenna half duplex relay channel.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Information Theory, 2009

Discrete-time, cyclostationary phase-locked loop model for jitter analysis.

[BibT_eX]

[DOI]

Sokratis D. Vamvakos

Vladimir Stojanovic

Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

A 1.5GS/s 4096-point digital spectrum analyzer for space-borne applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

Fixed- and variable-length ring oscillators for variability characterization in 45nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

2008

Error floors in LDPC codes: Fast simulation, bounds and hardware emulation.

[BibT_eX]

[DOI]

Proceedings of the 2008 IEEE International Symposium on Information Theory, 2008

Lowering LDPC Error Floors by Postprocessing.

[BibT_eX]

[DOI]

Proceedings of the Global Communications Conference, 2008. GLOBECOM 2008, New Orleans, LA, USA, 30 November, 2008

A 15 MHz - 600 MHz, 20 mW, 0.38 mm2, fast coarse locking digital DLL in 0.13μm CMOS.

[BibT_eX]

[DOI]

Sebastian Hoyos

Cheongyuen W. Tsang

Johan P. Vanderhaegen

Proceedings of the ESSCIRC 2008, 2008

Background ADC calibration in digital domain.

[BibT_eX]

[DOI]

Cheongyuen W. Tsang

Yun Chiu

Johan P. Vanderhaegen

Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

Measurement and analysis of variability in 45nm strained-Si CMOS technology.

[BibT_eX]

[DOI]

Liang-Teck Pang

Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

Compensation of systematic variations through optimal biasing of SRAM wordlines.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007

Power and Area Minimization for Multidimensional Signal Processing.

[BibT_eX]

[DOI]

Dejan Markovic

Robert W. Brodersen

IEEE J. Solid State Circuits, 2007

Peak-to-Average Power Ratio Reduction in an FDM Broadcast System.

[BibT_eX]

[DOI]

Proceedings of the IEEE Workshop on Signal Processing Systems, 2007

Power-Limited Design.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Conference on Electronics, 2007

Quantization Effects in Low-Density Parity-Check Decoders.

[BibT_eX]

[DOI]

Proceedings of IEEE International Conference on Communications, 2007

Analysis of Absorbing Sets for Array-Based LDPC Codes.

[BibT_eX]

[DOI]

Proceedings of IEEE International Conference on Communications, 2007

Fresh air: the emerging landscape of design for networked embedded systems.

[BibT_eX]

[DOI]

Radu Marculescu

Alberto L. Sangiovanni-Vincentelli

Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, 2007

ASIC Design and Verification in an FPGA Environment.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006

L. Embedding Mixed-Signal Design in Systems-on-Chip.

[BibT_eX]

[DOI]

Jan M. Rabaey

Fernando De Bernardinis

Ali M. Niknejad

Alberto L. Sangiovanni-Vincentelli

Proc. IEEE, 2006

Power - Performance Optimization for Custom Digital Circuits.

[BibT_eX]

[DOI]

J. Low Power Electron., 2006

A 240ps 64b carry-lookahead adder in 90nm CMOS.

[BibT_eX]

[DOI]

Sean Kao

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

Power and Area Efficient VLSI Architectures for Communication Signal Processing.

[BibT_eX]

[DOI]

Dejan Markovic

Robert W. Brodersen

Proceedings of IEEE International Conference on Communications, 2006

Investigation of Error Floors of Structured Low-Density Parity-Check Codes by Hardware Emulation.

[BibT_eX]

[DOI]

Proceedings of the Global Telecommunications Conference, 2006. GLOBECOM '06, San Francisco, CA, USA, 27 November, 2006

2005

FinFET-based SRAM design.

[BibT_eX]

[DOI]

Zheng Guo

Sriram Balasubramanian

Tsu-Jae King

Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

Scaling of analog-to-digital converters into ultra-deep-submicron CMOS.

[BibT_eX]

[DOI]

Yun Chiu

Paul R. Gray

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2004

Level conversion for dual-supply systems.

[BibT_eX]

[DOI]

Fujio Ishihara

Farhana Sheikh

IEEE Trans. Very Large Scale Integr. Syst., 2004

Least mean square adaptive digital background calibration of pipelined analog-to-digital converters.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2004

A shared-well dual-supply-voltage 64-bit ALU.

[BibT_eX]

[DOI]

Yasuhisa Shimazaki

IEEE J. Solid State Circuits, 2004

Methods for true energy-performance optimization.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2004

A 14-b 12-MS/s CMOS pipeline ADC with over 100-dB SFDR.

[BibT_eX]

[DOI]

Yun Chiu

Paul R. Gray

IEEE J. Solid State Circuits, 2004

Phase-locked loop architecture for adaptive jitter optimization.

[BibT_eX]

Sokratis D. Vamvakos

Carl Werner

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Low-density parity-check code constructions for hardware implementation.

[BibT_eX]

[DOI]

Edward Liao

Engling Yeo

Proceedings of IEEE International Conference on Communications, 2004

2003

A 500-Mb/s soft-output Viterbi decoder.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2003

Rapid Design and Analysis of Communication Systems Using the BEE Hardware Emulation Environment.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Workshop on Rapid System Prototyping (RSP 2003), 2003

Power-performance optimal 64-bit carry-lookahead adders.

[BibT_eX]

[DOI]

Proceedings of the ESSCIRC 2003, 2003

2002

A design environment for high-throughput low-power dedicated signal processing systems.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2002

Combining Dual-Supply, Dual-Threshold and Transistor Sizing for Power Reduction.

[BibT_eX]

[DOI]

Stephanie Augsburger

Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

Methods for true power minimization.

[BibT_eX]

[DOI]

Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

2001

Reduced complexity sequence detection for high-order partial response channels.

[BibT_eX]

[DOI]

IEEE J. Sel. Areas Commun., 2001

Analysis and design of low-energy flip-flops.

[BibT_eX]

[DOI]

Dejan Markovic

Robert W. Brodersen

Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

High throughput low-density parity-check decoder architectures.

[BibT_eX]

[DOI]

Proceedings of the Global Telecommunications Conference, 2001

List Viterbi decoding with continuous error detection for magnetic recording.

[BibT_eX]

[DOI]

Dragan Petrovic

Alberto L. Sangiovanni-Vincentelli

Kannan Ramchandran

Proceedings of the Global Telecommunications Conference, 2001

Design methodology for PicoRadio networks.

[BibT_eX]

[DOI]

Julio Leao da Silva Jr.

Paul K. Wright

Proceedings of the Conference on Design, Automation and Test in Europe, 2001

Achieving 550Mhz in an ASIC Methodology.

[BibT_eX]

[DOI]

David G. Chinnery

Kurt Keutzer

Proceedings of the 38th Design Automation Conference, 2001

A design environment for high throughput, low power dedicated signal processing systems.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001

2000

Clocked CMOS adiabatic logic with integrated single-phase power-clock supply.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2000

Improved sense-amplifier-based flip-flop: design and measurements.

[BibT_eX]

[DOI]

Michael Ming-Tak Leung

IEEE J. Solid State Circuits, 2000

1999

A rate 8/9 sliding block trellis code with stationary detector for magnetic recording.

[BibT_eX]

[DOI]