Borivoje Nikolic

Affiliations:
  • University of California, Berkeley, USA


According to our database1, Borivoje Nikolic authored at least 161 papers between 1997 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Awards

IEEE Fellow

IEEE Fellow 2017, "For contributions to energy-efficient design of digital and mixed-signal circuits".

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2022
An Eight-Core 1.44-GHz RISC-V Vector Processor in 16-nm FinFET.
IEEE J. Solid State Circuits, 2022

Design Techniques for a 6.4-32-Gb/s 0.96-pJ/b Continuous-Rate CDR With Stochastic Frequency-Phase Detector.
IEEE J. Solid State Circuits, 2022

Guest Editorial Introduction to the Special Issue on the 2021 Symposium on VLSI Circuits.
IEEE J. Solid State Circuits, 2022

2021
LAYGO: A Template-and-Grid-Based Layout Generation Engine for Advanced CMOS Technologies.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Accessible, FPGA Resource-Optimized Simulation of Multiclock Systems in FireSim.
IEEE Micro, 2021

A 71-to-86-GHz 16-Element by 16-Beam Multi-User Beamforming Integrated Receiver Sub-Array for Massive MIMO.
IEEE J. Solid State Circuits, 2021

Improved Processor Design Project Testing.
Proceedings of the ACM/IEEE Workshop on Computer Architecture Education, 2021

A Scalable Generator for Massive MIMO Baseband Processing Systems with Beamspace Channel Estimation.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2021

A Hardware Accelerator for Protocol Buffers.
Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021

4.3 An Eight-Core 1.44GHz RISC-V Vector Machine in 16nm FinFET.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

14.1 A 71-to-86GHz Packaged 16-Element by 16-Beam Multi-User Beamforming Integrated Receiver in 28nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

Memory-Efficient Hardware Performance Counters with Approximate-Counting Algorithms.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2021

Vertically Integrated Computing Labs Using Open-Source Hardware Generators and Cloud-Hosted FPGAs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

A Scalable Massive MIMO Uplink Baseband Processing Generator.
Proceedings of the ICC 2021, 2021

A 16mm<sup>2</sup> 106.1 GOPS/W Heterogeneous RISC-V Multi-Core Multi-Accelerator SoC in Low-Power 22nm FinFET.
Proceedings of the 47th ESSCIRC 2021, 2021

An Automated and Process-Portable Generator for Phase-Locked Loop.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

Gemmini: Enabling Systematic Deep-Learning Architecture Evaluation via Full-Stack Integration.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020
A Dual-Core RISC-V Vector Processor With On-Chip Fine-Grain Power Management in 28-nm FD-SOI.
IEEE Trans. Very Large Scale Integr. Syst., 2020

Chipyard: Integrated Design, Simulation, and Implementation Framework for Custom SoCs.
IEEE Micro, 2020

Wireless Channel Dynamics for Relay Selection under Ultra-Reliable Low-Latency Communication.
Proceedings of the 31st IEEE Annual International Symposium on Personal, 2020

A Methodology for Reusable Physical Design.
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020

Design and Demonstration of a Scalable Massive MIMO Uplink at E-Band.
Proceedings of the 2020 IEEE International Conference on Communications Workshops, 2020

AutoCkt: Deep Reinforcement Learning of Analog Circuit Designs.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Invited: Chipyard - An Integrated SoC Research and Implementation Environment.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

FirePerf: FPGA-Accelerated Full-System Hardware/Software Performance Profiling and Co-Design.
Proceedings of the ASPLOS '20: Architectural Support for Programming Languages and Operating Systems, 2020

2019
FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud.
IEEE Micro, 2019

BROOM: An Open-Source Out-of-Order Processor With Resilient Low-Voltage Operation in 28-nm CMOS.
IEEE Micro, 2019

A Real-Time, 1.89-GHz Bandwidth, 175-kHz Resolution Sparse Spectral Analysis RISC-V SoC in 16-nm FinFET.
IEEE J. Solid State Circuits, 2019

A Mixed-Signal RISC-V Signal Analysis SoC Generator With a 16-nm FinFET Instance.
IEEE J. Solid State Circuits, 2019

Wireless Channel Dynamics and Robustness for Ultra-Reliable Low-Latency Communications.
IEEE J. Sel. Areas Commun., 2019

Gemmini: An Agile Systolic Array Generator Enabling Systematic Evaluations of Deep-Learning Architectures.
CoRR, 2019

RTL bug localization through LTL specification mining (WIP).
Proceedings of the 17th ACM-IEEE International Conference on Formal Methods and Models for System Design, 2019

Open-Source EDA Tools and IP, A View from the Trenches.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

A Generated 7GS/s 8b Time-Interleaved SAR ADC with 38.2dB SNDR at Nyquist in 16nm CMOS FinFET.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

A 3.01 mm<sup>2</sup> 65.38Gb/s Stochastic LDPC Decoder for IEEE 802.3an in 65 nm.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019

2018
A Variation-Tolerant, Sneak-Current-Compensated Readout Scheme for Cross-Point Memory Based on Two-Port Sensing Technique.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

A 65-nm CMOS <i>I/Q</i> RF Power DAC With 24- to 42-dB Third-Harmonic Cancellation and Up to 18-dB Mixed-Signal Filtering.
IEEE J. Solid State Circuits, 2018

Network Coding for Real-time Wireless Communication for Automation.
CoRR, 2018

A Dual-Mode Configurable RF-to-Digital Receiver in 16NM FinFET.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

An Out-of-Order RISC-V Processor with Resilient Low-Voltage Operation in 28NM CMOS.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

Predicting Wireless Channels for Ultra-Reliable Low-Latency Communications.
Proceedings of the 2018 IEEE International Symposium on Information Theory, 2018

Energy-Efficient Design in FDSOI.
Proceedings of the 48th European Solid-State Device Research Conference, 2018

A Real-Time, Analog/Digital Co-Designed 1.89-GHz Bandwidth, 175-kHz Resolution Sparse Spectral Analysis RISC-V SoC in 16-nm FinFET.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018

Generating the Next Wave of Custom Silicon.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018

ACED: a hardware library for generating DSP systems.
Proceedings of the 55th Annual Design Automation Conference, 2018

BAG2: A process-portable framework for generator-based AMS circuit design.
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018

A 28nm FDSOI 8192-point digital ASIC spectrometer from a Chisel generator.
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018


2017
Real-Time Cooperative Communication for Automation Over Wireless.
IEEE Trans. Wirel. Commun., 2017

Use of Phase Delay Analysis for Evaluating Wideband Circuits: An Alternative to Group Delay Analysis.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Reprogrammable Redundancy for SRAM-Based Cache V<sub>min</sub> Reduction in a 28-nm RISC-V Processor.
IEEE J. Solid State Circuits, 2017

A 65-nm CMOS Wideband TDD Front-End With Integrated T/R Switching via PA Re-Use.
IEEE J. Solid State Circuits, 2017

A RISC-V Processor SoC With Integrated Power Management at Submicrosecond Timescales in 28 nm FD-SOI.
IEEE J. Solid State Circuits, 2017

Analysis and Design of Integrated Active Cancellation Transceiver for Frequency Division Duplex Systems.
IEEE J. Solid State Circuits, 2017

A yield optimization methodology for mixed-signal circuits.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

A 0.37mm<sup>2</sup> LTE/Wi-Fi compatible, memory-based, runtime-reconfigurable 2<sup>n</sup>3<sup>m</sup>5<sup>k</sup> FFT accelerator integrated with a RISC-V core in 16nm FinFET.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017

A low-voltage low-offset dual strong-arm latch comparator.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017

On-chip spur and phase noise cancellation techniques.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017

2016
Design of Energy- and Cost-Efficient Massive MIMO Arrays.
Proc. IEEE, 2016

A RISC-V Vector Processor With Simultaneous-Switching Switched-Capacitor DC-DC Converters in 28 nm FDSOI.
IEEE J. Solid State Circuits, 2016

A Self-Adjustable Clock Generator With Wide Dynamic Range in 28 nm FDSOI.
IEEE J. Solid State Circuits, 2016

Cooperative Communication for Control over Wireless.
CoRR, 2016

Network coding for high-reliability low-latency wireless control.
Proceedings of the IEEE Wireless Communications and Networking Conference Workshops, 2016

A 65nm CMOS transceiver with integrated active cancellation supporting FDD from 1GHz to 1.8GHz at +12.6dBm TX power leakage.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

A fast, flexible, positive and negative adaptive body-bias generator in 28nm FDSOI.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

Phase noise scaling and tracking in OFDM multi-user beamforming arrays.
Proceedings of the 2016 IEEE International Conference on Communications, 2016

A generator of memory-based, runtime-reconfigurable 2N3M5K FFT engines.
Proceedings of the 2016 IEEE International Conference on Acoustics, 2016

On-chip I-V variability and random telegraph noise characterization in 28 nm CMOS.
Proceedings of the 46th European Solid-State Device Research Conference, 2016

A 65nm CMOS wideband TDD front-end with integrated T/R switching via PA re-use.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016

Sub-microsecond adaptive voltage scaling in a 28nm FD-SOI processor SoC.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016

Reprogrammable redundancy for cache Vmin reduction in a 28nm RISC-V processor.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

On-chip supply power measurement and waveform reconstruction in a 28nm FD-SOI processor SoC.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

A double-tail sense amplifier for low-voltage SRAM in 28nm technology.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2015
Per-Core DVFS With Switched-Capacitor Converters for Energy Efficiency in Manycore Processors.
IEEE Trans. Very Large Scale Integr. Syst., 2015

A Differential 2R Crosspoint RRAM Array With Zero Standby Current.
IEEE Trans. Circuits Syst. II Express Briefs, 2015

A RISC-V vector processor with tightly-integrated switched-capacitor DC-DC converters in 28nm FDSOI.
Proceedings of the Symposium on VLSI Circuits, 2015

Design considerations for low-noise transconductance amplifiers in 28nm UTBB-FDSOI.
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

F1: High-speed interleaved ADCs.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

Cooperative communication for high-reliability low-latency wireless control.
Proceedings of the 2015 IEEE International Conference on Communications, 2015

A scalable massive MIMO array architecture based on common modules.
Proceedings of the IEEE International Conference on Communication, 2015

Raven: A 28nm RISC-V vector processor with integrated switched-capacitor DC-DC converters and adaptive clocking.
Proceedings of the 2015 IEEE Hot Chips 27 Symposium (HCS), 2015

Simpler, more efficient design.
Proceedings of the ESSCIRC Conference 2015, 2015

A 550-2260MHz self-adjustable clock generator in 28nm FDSOI.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015

2014
A Wideband 400 MHz-to-4 GHz Direct RF-to-Digital Multimode ΔΣ Receiver.
IEEE J. Solid State Circuits, 2014

27.7 A scalable 1.5-to-6Gb/s 6.2-to-38.1mW LDPC decoder for 60GHz wireless networks in 28nm UTBB FDSOI.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

Design of a low-latency, high-reliability wireless communication system for control applications.
Proceedings of the IEEE International Conference on Communications, 2014

Joint impact of random variations and RTN on dynamic writeability in 28nm bulk and FDSOI SRAM.
Proceedings of the 44th European Solid State Device Research Conference, 2014

A frequency-reconfigurable multi-standard 65nm CMOS digital transmitter with LTCC interposers.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014

2013
A 2.8 GS/s 44.6 mW Time-Interleaved ADC Achieving 50.9 dB SNDR and 3 dB Effective Resolution Bandwidth of 1.5 GHz in 65 nm CMOS.
IEEE J. Solid State Circuits, 2013

Coding and System Design for Quantize-Map-and-Forward Relaying.
IEEE J. Sel. Areas Commun., 2013

Relay scheduling and interference cancellation for quantize-map-and-forward cooperative relaying.
Proceedings of the 2013 IEEE International Symposium on Information Theory, 2013

A 0.4 GHz - 4 GHz direct RF-to-digital ΣΔ multi-mode receiver.
Proceedings of the ESSCIRC 2013, 2013

2012
A 15 MHz to 600 MHz, 20 mW, 0.38 mm<sup>2</sup> Split-Control, Fast Coarse Locking Digital DLL in 0.13 µ m CMOS.
IEEE Trans. Very Large Scale Integr. Syst., 2012

SRAM Assist Techniques for Operation in a Wide Voltage Range in 28-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2012

A 2.8GS/s 44.6mW time-interleaved ADC achieving 50.9dB SNDR and 3dB effective resolution bandwidth of 1.5GHz in 65nm CMOS.
Proceedings of the Symposium on VLSI Circuits, 2012

2011
Discrete-Time, Linear Periodically Time-Variant Phase-Locked Loop Model for Jitter Analysis.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

Technology Variability From a Design Perspective.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

Characterization of Dynamic SRAM Stability in 45 nm CMOS.
IEEE J. Solid State Circuits, 2011

A 2 Gb/s 5.6 mW Digital LOS/NLOS Equalizer for the 60 GHz Band.
IEEE J. Solid State Circuits, 2011

LDPC decoder architecture for high-data rate personal-area networks.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Managing variability for ultimate energy efficiency.
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011

2010
SRAM Read/Write Margin Enhancements Using FinFETs.
IEEE Trans. Very Large Scale Integr. Syst., 2010

Analysis of absorbing sets and fully absorbing sets of array-based LDPC codes.
IEEE Trans. Inf. Theory, 2010

An Efficient 10GBASE-T Ethernet LDPC Decoder Design With Low Error Floors.
IEEE J. Solid State Circuits, 2010

SRAM stability characterization using tunable ring oscillators in 45nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

SRAM design in fully-depleted SOI technology.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Parameter-specific ring oscillator for process monitoring at the 45 nm node.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

Technology variability from a design perspective.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2009
Design of LDPC decoders for improved low error rate performance: quantization and algorithm choices.
IEEE Trans. Commun., 2009

Energy-Delay Optimization of 64-Bit Carry-Lookahead Adders With a 240 ps 90 nm CMOS Design Example.
IEEE J. Solid State Circuits, 2009

Measurement and Analysis of Variability in 45 nm Strained-Si CMOS Technology.
IEEE J. Solid State Circuits, 2009

Measurements and Analysis of Process Variability in 90nmCMOS.
IEEE J. Solid State Circuits, 2009

Large-Scale SRAM Variability Characterization in 45 nm CMOS.
IEEE J. Solid State Circuits, 2009

Predicting error floors of structured LDPC codes: deterministic bounds and estimates.
IEEE J. Sel. Areas Commun., 2009

Cooperative multiplexing in the multiple antenna half duplex relay channel.
Proceedings of the IEEE International Symposium on Information Theory, 2009

Discrete-time, cyclostationary phase-locked loop model for jitter analysis.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

A 1.5GS/s 4096-point digital spectrum analyzer for space-borne applications.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

Fixed- and variable-length ring oscillators for variability characterization in 45nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

2008
Error floors in LDPC codes: Fast simulation, bounds and hardware emulation.
Proceedings of the 2008 IEEE International Symposium on Information Theory, 2008

Lowering LDPC Error Floors by Postprocessing.
Proceedings of the Global Communications Conference, 2008. GLOBECOM 2008, New Orleans, LA, USA, 30 November, 2008

A 15 MHz - 600 MHz, 20 mW, 0.38 mm2, fast coarse locking digital DLL in 0.13μm CMOS.
Proceedings of the ESSCIRC 2008, 2008

Background ADC calibration in digital domain.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

Measurement and analysis of variability in 45nm strained-Si CMOS technology.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

Compensation of systematic variations through optimal biasing of SRAM wordlines.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007
Power and Area Minimization for Multidimensional Signal Processing.
IEEE J. Solid State Circuits, 2007

Peak-to-Average Power Ratio Reduction in an FDM Broadcast System.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2007

Power-Limited Design.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

Quantization Effects in Low-Density Parity-Check Decoders.
Proceedings of IEEE International Conference on Communications, 2007

Analysis of Absorbing Sets for Array-Based LDPC Codes.
Proceedings of IEEE International Conference on Communications, 2007

Fresh air: the emerging landscape of design for networked embedded systems.
Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, 2007

ASIC Design and Verification in an FPGA Environment.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006
L. Embedding Mixed-Signal Design in Systems-on-Chip.
Proc. IEEE, 2006

Power - Performance Optimization for Custom Digital Circuits.
J. Low Power Electron., 2006

A 240ps 64b carry-lookahead adder in 90nm CMOS.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

Power and Area Efficient VLSI Architectures for Communication Signal Processing.
Proceedings of IEEE International Conference on Communications, 2006

Investigation of Error Floors of Structured Low-Density Parity-Check Codes by Hardware Emulation.
Proceedings of the Global Telecommunications Conference, 2006. GLOBECOM '06, San Francisco, CA, USA, 27 November, 2006

2005
FinFET-based SRAM design.
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

Scaling of analog-to-digital converters into ultra-deep-submicron CMOS.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2004
Level conversion for dual-supply systems.
IEEE Trans. Very Large Scale Integr. Syst., 2004

Least mean square adaptive digital background calibration of pipelined analog-to-digital converters.
IEEE Trans. Circuits Syst. I Regul. Pap., 2004

A shared-well dual-supply-voltage 64-bit ALU.
IEEE J. Solid State Circuits, 2004

Methods for true energy-performance optimization.
IEEE J. Solid State Circuits, 2004

A 14-b 12-MS/s CMOS pipeline ADC with over 100-dB SFDR.
IEEE J. Solid State Circuits, 2004

Phase-locked loop architecture for adaptive jitter optimization.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Low-density parity-check code constructions for hardware implementation.
Proceedings of IEEE International Conference on Communications, 2004

2003
A 500-Mb/s soft-output Viterbi decoder.
IEEE J. Solid State Circuits, 2003

Rapid Design and Analysis of Communication Systems Using the BEE Hardware Emulation Environment.
Proceedings of the 14th IEEE International Workshop on Rapid System Prototyping (RSP 2003), 2003

2002
A design environment for high-throughput low-power dedicated signal processing systems.
IEEE J. Solid State Circuits, 2002

Combining Dual-Supply, Dual-Threshold and Transistor Sizing for Power Reduction.
Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

Methods for true power minimization.
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

2001
Reduced complexity sequence detection for high-order partial response channels.
IEEE J. Sel. Areas Commun., 2001

Analysis and design of low-energy flip-flops.
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

High throughput low-density parity-check decoder architectures.
Proceedings of the Global Telecommunications Conference, 2001

List Viterbi decoding with continuous error detection for magnetic recording.
Proceedings of the Global Telecommunications Conference, 2001

Design methodology for PicoRadio networks.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

Achieving 550Mhz in an ASIC Methodology.
Proceedings of the 38th Design Automation Conference, 2001

2000
Clocked CMOS adiabatic logic with integrated single-phase power-clock supply.
IEEE Trans. Very Large Scale Integr. Syst., 2000

Improved sense-amplifier-based flip-flop: design and measurements.
IEEE J. Solid State Circuits, 2000

1999
A rate 8/9 sliding block trellis code with stationary detector for magnetic recording.
Proceedings of the 1999 IEEE International Conference on Communications: Global Convergence Through Communications, 1999

1998
CMOS implementation of low-power oscillators based on the modified Fabre-Normand current conveyor.
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998

1997
Clocked CMOS adiabatic logic with integrated single-phase power-clock supply: experimental results.
Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997


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