John P. KeaneAffiliations:
- Keysight Technologies, Santa Clara, CA, USA
- University of California, Davis, CA, USA (former)
According to our database1, John P. Keane authored at least 8 papers between 2004 and 2020.
Legend:Book In proceedings Article PhD thesis Other
Introduction to the Special Issue on the 2020 IEEE International Solid-State Circuits Conference (ISSCC).
IEEE J. Solid State Circuits, 2020
16.5 An 8GS/s time-interleaved SAR ADC with unresolved decision detection achieving -58dBFS noise and 4GHz bandwidth in 28nm CMOS.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
IEEE Trans. Circuits Syst. II Express Briefs, 2015
A 14b 2.5GS/s 8-way-interleaved pipelined ADC with background calibration and digital dynamic linearity correction.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
Digital background calibration for memory effects in pipelined analog-to-digital converters.
IEEE Trans. Circuits Syst. I Regul. Pap., 2006
IEEE Trans. Circuits Syst. I Regul. Pap., 2005
Convergence analysis of a background interstage gain calibration technique for pipelined ADCs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Miller compensation using current buffers in fully differential CMOS two-stage operational amplifiers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2004