Echere Iroaga

According to our database, Echere Iroaga authored at least 4 papers between 2005 and 2018.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2018

Clock Synchronous Reset and Skew Calibration of 65GS/s ADCs in A Multi-Lane Coherent Receiver.

Shankarram Athreya, Hiva Hedayati, Shayan Kazemkhani, Yanfei Chen, Saurabh Vats, Michael D. Scott, Bart Zeydel, Peter Keller, Jian Wang, Bhaskarareddy Avula, Boris Murmann, Echere Iroaga

Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018

2007

A 12-Bit 75-MS/s Pipelined ADC Using Incomplete Settling.

Echere Iroaga, Boris Murmann

IEEE J. Solid State Circuits, 2007

2005

A background correction technique for timing errors in time-interleaved analog-to-digital converters.

Echere Iroaga, Boris Murmann, L. Y. Nathawad

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A low-power distributed wide-band LNA in 0.18µm CMOS.

Srikanth Arekapudi, Echere Iroaga, Boris Murmann

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005