Saurabh Vats

According to our database, Saurabh Vats authored at least 3 papers between 2012 and 2018.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2018

Clock Synchronous Reset and Skew Calibration of 65GS/s ADCs in A Multi-Lane Coherent Receiver.

Shankarram Athreya, Hiva Hedayati, Shayan Kazemkhani, Yanfei Chen, Saurabh Vats, Michael D. Scott, Bart Zeydel, Peter Keller, Jian Wang, Bhaskarareddy Avula, Boris Murmann, Echere Iroaga

Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018

2014

Selection of optimal electronic toll collection system for India: A subjective-fuzzy decision making approach.

Saurabh Vats, Gaurav Vats, Rahul Vaish, Varun Kumar

Appl. Soft Comput., 2014

2012

A sub-2W 10GBase-T analog front-end in 40nm CMOS process.

Tarun Gupta, Frank Yang, Dong Wang, Ali Tabatabaei, Ramesh Singh, Hesam Amir Aslanzadeh, Alireza Khalili, Saurabh Vats, Susan Arno, Sean Campeau

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012