Saurabh Vats

According to our database, Saurabh Vats authored at least 6 papers between 2012 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2026

A 56-Gb/s Hybrid Silicon Photonic and 5-nm CMOS 3-D-Integrated Transceiver for Optical Compute I/O.

Ganesh Balamurugan, Parmanand Mishra, Subal Sahni, Ankur Aggarwal, Simon Forey, Andrew Gimlett, Prateek Goyal, Han Hao, Santosh Hariwan, Masum Hossain, Sejun Jeon, Narayan Kaniyur, David Lazovsky, Wonho Lee, Bengt Littmann, Raj Nagulapalli, Kevin Park, John Rollinson, Matteo Staffaroni, Prakash Thakur, Saurabh Vats, Preet Virk, Dehua Xiao, Hemesh Yasotharan, Raman Yazdani, Waleed Younis, Shifeng Yu, Phil Winterbottom

IEEE J. Solid State Circuits, April, 2026

2025

Photonic Fabric for Memory and Compute Disaggregation.

Subal Sahni, Ankur Aggarwal, Nadav Bergstein, Trung Diep, Jing Ding, Andrew Gimlett, Ravi Mahatme, Parmanand Mishra, Sujit Ramachandra, Matteo Staffaroni, Angelina Totovic, Saurabh Vats, Phil Winterbottom, Waleed Younis, Shifeng Yu, David Lazovsky

Proceedings of the Optical Fiber Communications Conference and Exhibition, 2025

2024

Beyond the Beachfront: Integration of Silicon Photonic I/Os under a High-Power ASIC.

Subal Sahni, Abhijit Abhyankar, Ankur Aggarwal, Nikos Bamiedakis, Zoltan Bekker, Mohamed Benromdhane, Nadav Bergstein, Ties Bos, Christopher Davies, Andrew Gimlett, Xiaoping Han, Kelin Lee, Kavya Mahadevaiah, Hakki Ozguc, Kevin Park, Jeremy Plunkett, Sujit Ramachandra, Jason Redgrave, Ajmer Singh, Matteo Staffaroni, Angelina Totovic, Saurabh Vats, Phil Winterbottom, Darren Woodhouse, Waleed Younis, Shifeng Yu, David Lazovsky

Proceedings of the Optical Fiber Communications Conference and Exhibition, 2024

2018

Clock Synchronous Reset and Skew Calibration of 65GS/s ADCs in A Multi-Lane Coherent Receiver.

Shankarram Athreya, Hiva Hedayati, Shayan Kazemkhani, Yanfei Chen, Saurabh Vats, Michael D. Scott, Bart Zeydel, Peter Keller, Jian Wang, Bhaskarareddy Avula, Boris Murmann, Echere Iroaga

Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018

2014

Selection of optimal electronic toll collection system for India: A subjective-fuzzy decision making approach.

Saurabh Vats, Gaurav Vats, Rahul Vaish, Varun Kumar

Appl. Soft Comput., 2014

2012

A sub-2W 10GBase-T analog front-end in 40nm CMOS process.

Tarun Gupta, Frank Yang, Dong Wang, Ali Tabatabaei, Ramesh Singh, Hesam Amir Aslanzadeh, Alireza Khalili, Saurabh Vats, Susan Arno, Sean Campeau

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012