Eike Schmidt

According to our database1, Eike Schmidt authored at least 14 papers between 1999 and 2022.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2022

2007
System level clock tree synthesis for power optimization.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2004
Leakage in CMOS Circuits - An Introduction.
Proceedings of the Integrated Circuit and System Design, 2004

2003
Power modeling of embedded memories.
PhD thesis, 2003

2002
Memory power models for multilevel power estimation and optimization.
IEEE Trans. Very Large Scale Integr. Syst., 2002

An Improved Power Macro-Model for Arithmetic Datapath Components.
Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002

2001
Estimation of lower and upper bounds on the power consumption from scheduled data flow graphs.
IEEE Trans. Very Large Scale Integr. Syst., 2001

System level optimization and design space exploration for low power.
Proceedings of the 14th International Symposium on Systems Synthesis, 2001

Automatic nonlinear memory power modelling.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

2000
Power Macro-Modelling for Firm-Macro.
Proceedings of the Integrated Circuit Design, 2000

Lower Bound Estimation for Low Power High-Level Synthesis.
Proceedings of the 13th International Symposium on System Synthesis, 2000

Lower Bounds on the Power Consumption in Scheduled Data Flow Graphs with Resource Constraints.
Proceedings of the 2000 Design, 2000

1999
Lower and upper bounds on the switching activity in scheduled data flow graphs.
Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999

A New Parameterizable Power Macro-Model for Datapath Components.
Proceedings of the 1999 Design, 1999


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