Domenik Helms

According to our database1, Domenik Helms authored at least 24 papers between 2002 and 2018.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2018
Leakage Models for High-Level Power Estimation.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

2017
User dependent aging prediction model for automotive controllers with power electronics.
Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017

Timing modeling at RT-level by separation of design- and stress related aging impacts.
Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017

2016
Analysis of NBTI effects on high frequency digital circuits.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

RT level timing modeling for aging prediction.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2014
Efficient NBTI modeling technique considering recovery effects.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014

Using Early Power and Timing Estimations of Massively Heterogeneous Computation Platforms to Create Optimized HPC Applications.
Proceedings of the 12th IEEE International Conference on Embedded and Ubiquitous Computing, 2014

2013
Profilbasierte Energieabschätzung integrierter Schaltungen auf algorithmischer Ebene.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2013

Early Power & Timing Estimation of Custom Hardware Blocks based on Automatically Generated Combinatorial Macros.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2013

2012
Phase Space Based NBTI Model.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2012

2009
RTL power modeling and estimation of sleep transistor based power gating.
J. Embedded Computing, 2009

Hybrid logical-statistical simulation with thermal and IR-drop mapping for degradation and variation prediction.
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009

2008
A Comparison of Approaches for High-Level Power Estimation of LUT-Based DSP Components.
Proceedings of the ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 2008

On leakage currents: sources and reduction for transistors, gates, memories and digital systems.
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008

2007
Modelling the Impact of High Level Leakage Optimization Techniques on the Delay of RT-Components.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007

Voltage- and ABB-island optimization in high level synthesis.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

Logic design techniques for 65 to 45nm and below for reducing total energy and solving technology variations problems.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

2006
Accurate PTV, State, and ABB Aware RTL Blackbox Modeling of Subthreshold, Gate, and PN-Junction Leakage.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

Analysis and modeling of subthreshold leakage of RT-components under PTV and state variation.
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006

2005
A High Level Constant Coefficient Multiplier Power Model for Power Estimation on High Levels of Abstraction.
Proceedings of the Integrated Circuit and System Design, 2005

2004
Leakage in CMOS Circuits - An Introduction.
Proceedings of the Integrated Circuit and System Design, 2004

2003
Interconnect Driven Low Power High-Level Synthesis.
Proceedings of the Integrated Circuit and System Design, 2003

Binding, Allocation and Floorplanning in Low Power High-Level Synthesis.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

2002
An Improved Power Macro-Model for Arithmetic Datapath Components.
Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002


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