Domenik Helms

According to our database, Domenik Helms authored at least 31 papers between 2002 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

Fast Yet Accurate Timing and Power Prediction of Artificial Neural Networks Deployed on Clock-Gated Multi-Core Platforms.

Quentin Dariol, Sébastien Le Nours, Domenik Helms, Ralf Stemmer, Sébastien Pillement, Kim Grüttner

Proceedings of the DroneSE and RAPIDO: System Engineering for constrained embedded systems, 2023

2022

A Hybrid Performance Prediction Approach for Fully-Connected Artificial Neural Networks on Multi-core Platforms.

Quentin Dariol, Sébastien Le Nours, Sébastien Pillement, Ralf Stemmer, Domenik Helms, Kim Grüttner

Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2022

Hardware Execution Time Prediction for Neural Network Layers.

Adrian Osterwind, Julian Droste-Rehling, Manoj Rohit Vemparala, Domenik Helms

Proceedings of the Machine Learning and Principles and Practice of Knowledge Discovery in Databases, 2022

Using Network Architecture Search for Optimizing Tensor Compression.

Arunachalam Thirunavukkarasu, Domenik Helms

Proceedings of the Designing Modern Embedded Systems: Software, Hardware, and Applications, 2022

Accelerating and pruning CNNs for semantic segmentation on FPGA.

Pierpaolo Morì, Manoj Rohit Vemparala, Nael Fasfous, Saptarshi Mitra, Sreetama Sarkar, Alexander Frickenstein, Lukas Frickenstein, Domenik Helms, Naveen Shankar Nagaraja, Walter Stechele, Claudio Passerone

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2020

An Embedded CNN Implementation for On-Device ECG Analysis.

Alwyn Burger, Chao Qian, Gregor Schiele, Domenik Helms

Proceedings of the 2020 IEEE International Conference on Pervasive Computing and Communications Workshops, 2020

2018

Leakage Models for High-Level Power Estimation.

Domenik Helms, Reef Eilers, Malte Metzdorf, Wolfgang Nebel

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

2017

User dependent aging prediction model for automotive controllers with power electronics.

Sunil Malipatlolla, Ahmet Unutulmaz, Domenik Helms, Wolfgang Nebel

Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017

Timing modeling at RT-level by separation of design- and stress related aging impacts.

Nils Koppaetzky, Malte Metzdorf, Reef Eilers, Domenik Helms, Wolfgang Nebel

Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017

2016

Analysis of NBTI effects on high frequency digital circuits.

Ahmet Unutulmaz, Domenik Helms, Reef Eilers, Malte Metzdorf, Ben Kaczer, Wolfgang Nebel

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

RT level timing modeling for aging prediction.

Nils Koppaetzky, Malte Metzdorf, Reef Eilers, Domenik Helms, Wolfgang Nebel

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2014

Efficient NBTI modeling technique considering recovery effects.

Reef Eilers, Malte Metzdorf, Domenik Helms, Wolfgang Nebel

Proceedings of the International Symposium on Low Power Electronics and Design, 2014

Using Early Power and Timing Estimations of Massively Heterogeneous Computation Platforms to Create Optimized HPC Applications.

Patrick Knocke, Ralph Görgen, Jörg Walter, Domenik Helms, Wolfgang Nebel

Proceedings of the 12th IEEE International Conference on Embedded and Ubiquitous Computing, 2014

2013

Profilbasierte Energieabschätzung integrierter Schaltungen auf algorithmischer Ebene.

Lars Kosmann, Axel Reimer, Domenik Helms, Wolfgang Nebel

Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2013

Early Power & Timing Estimation of Custom Hardware Blocks based on Automatically Generated Combinatorial Macros.

Kai Hylla, Philipp A. Hartmann, Domenik Helms, Wolfgang Nebel

Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2013

2012

Phase Space Based NBTI Model.

Reef Eilers, Malte Metzdorf, Sven Rosinger, Domenik Helms, Wolfgang Nebel

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2012

2011

Behavioral-level thermal- and aging-estimation flow.

Sven Rosinger, Malte Metzdorf, Domenik Helms, Wolfgang Nebel

Proceedings of the 12th Latin American Test Workshop, 2011

2009

RTL power modeling and estimation of sleep transistor based power gating.

Sven Rosinger, Domenik Helms, Wolfgang Nebel

J. Embed. Comput., 2009

Hybrid logical-statistical simulation with thermal and IR-drop mapping for degradation and variation prediction.

Domenik Helms, Kai Hylla, Wolfgang Nebel

Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009

2008

A Comparison of Approaches for High-Level Power Estimation of LUT-Based DSP Components.

Ruzica Jevtic, Carlos Carreras, Domenik Helms

Proceedings of the ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 2008

On leakage currents: sources and reduction for transistors, gates, memories and digital systems.

Wolfgang Nebel, Domenik Helms

Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008

2007

Modelling the Impact of High Level Leakage Optimization Techniques on the Delay of RT-Components.

Marko Hoyer, Domenik Helms, Wolfgang Nebel

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007

Voltage- and ABB-island optimization in high level synthesis.

Domenik Helms, Olaf Meyer, Marko Hoyer, Wolfgang Nebel

Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

Logic design techniques for 65 to 45nm and below for reducing total energy and solving technology variations problems.

Domenik Helms, Wolfgang Nebel

Proceedings of the 14th IEEE International Conference on Electronics, 2007

2006

Accurate PTV, State, and ABB Aware RTL Blackbox Modeling of Subthreshold, Gate, and PN-Junction Leakage.

Domenik Helms, Marko Hoyer, Wolfgang Nebel

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

Analysis and modeling of subthreshold leakage of RT-components under PTV and state variation.

Domenik Helms, Günter Ehmen, Wolfgang Nebel

Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006

2005

A High Level Constant Coefficient Multiplier Power Model for Power Estimation on High Levels of Abstraction.

Arne Schulz, Andreas Schallenberg, Domenik Helms, Milan Schulte, Axel Reimer, Wolfgang Nebel

Proceedings of the Integrated Circuit and System Design, 2005

2004

Leakage in CMOS Circuits - An Introduction.

Domenik Helms, Eike Schmidt, Wolfgang Nebel

Proceedings of the Integrated Circuit and System Design, 2004

2003

Interconnect Driven Low Power High-Level Synthesis.

Ansgar Stammermann, Domenik Helms, Milan Schulte, Arne Schulz, Wolfgang Nebel

Proceedings of the Integrated Circuit and System Design, 2003

Binding, Allocation and Floorplanning in Low Power High-Level Synthesis.

Ansgar Stammermann, Domenik Helms, Milan Schulte, Arne Schulz, Wolfgang Nebel

Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

2002

An Improved Power Macro-Model for Arithmetic Datapath Components.

Domenik Helms, Eike Schmidt, Arne Schulz, Ansgar Stammermann, Wolfgang Nebel

Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002