Lars Kruse

According to our database1, Lars Kruse authored at least 14 papers between 1998 and 2007.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Links

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Bibliography

2007
Early power grid verification under circuit current uncertainties.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

A geometric approach for early power grid verification using current constraints.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

2002
Memory power models for multilevel power estimation and optimization.
IEEE Trans. Very Large Scale Integr. Syst., 2002

2001
Estimation of lower and upper bounds on the power consumption from scheduled data flow graphs.
IEEE Trans. Very Large Scale Integr. Syst., 2001

System level optimization and design space exploration for low power.
Proceedings of the 14th International Symposium on Systems Synthesis, 2001

Estimating and optimizing power consumption of integrated macro blocks at the behavioral level.
Proceedings of the Ausgezeichnete Informatikdissertationen 2001, 2001

Automatic nonlinear memory power modelling.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

Estimating and optimizing power consumption of integrated macro blocks at the behavioral level.
PhD thesis, 2001

2000
Power Macro-Modelling for Firm-Macro.
Proceedings of the Integrated Circuit Design, 2000

Lower Bound Estimation for Low Power High-Level Synthesis.
Proceedings of the 13th International Symposium on System Synthesis, 2000

Lower Bounds on the Power Consumption in Scheduled Data Flow Graphs with Resource Constraints.
Proceedings of the 2000 Design, 2000

1999
Lower and upper bounds on the switching activity in scheduled data flow graphs.
Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999

A New Parameterizable Power Macro-Model for Datapath Components.
Proceedings of the 1999 Design, 1999

1998
Power-Simulation of Cell Based ASICs: Accuracy- and Performance Trade-Offs.
Proceedings of the 1998 Design, 1998


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