Enrico Macii

According to our database1, Enrico Macii authored at least 362 papers between 1991 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Awards

IEEE Fellow

IEEE Fellow 2006, "For contributions to power-efficient very large scaled integrated (VLSI) circuits and systems.".

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2018
Thermal Management of Batteries Using Supercapacitor Hybrid Architecture With Idle Period Insertion Strategy.
IEEE Trans. VLSI Syst., 2018

LAPSE: Low-Overhead Adaptive Power Saving and Contrast Enhancement for OLEDs.
IEEE Trans. Image Processing, 2018

Optimizing Network Traffic for Spiking Neural Network Simulations on Densely Interconnected Many-Core Neuromorphic Platforms.
IEEE Trans. Emerging Topics Comput., 2018

GIS-Based Software Infrastructure to Model PV Generation in Fine-Grained Spatio-Temporal Domain.
IEEE Systems Journal, 2018

Empirical derivation of upper and lower bounds of NBTI aging for embedded cores.
Microelectronics Reliability, 2018

Composable Battery Model Templates Based on Manufacturers' Data.
IEEE Design & Test, 2018

Aging and Cost Optimal Residential Charging for Plug-In EVs.
IEEE Design & Test, 2018

Distributed Infrastructure for Multi-Energy-Systems Modelling and Co-simulation in Urban Districts.
Proceedings of the 7th International Conference on Smart Cities and Green ICT Systems, 2018

Forecasting Short-term Solar Radiation for Photovoltaic Energy Predictions.
Proceedings of the 7th International Conference on Smart Cities and Green ICT Systems, 2018

Dynamic Bit-width Reconfiguration for Energy-Efficient Deep Learning Hardware.
Proceedings of the International Symposium on Low Power Electronics and Design, 2018

Battery-Aware Energy Model of Drone Delivery Tasks.
Proceedings of the International Symposium on Low Power Electronics and Design, 2018

Optimal Topology-Aware PV Panel Floorplanning with Hybrid Orientation.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

Battery-aware Design Exploration of Scheduling Policies for Multi-sensor Devices.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

IoT Software Infrastructure for Remote Monitoring of Patients with Chronic Metabolic Disorders.
Proceedings of the 6th IEEE International Conference on Future Internet of Things and Cloud, 2018

GIS-based optimal photovoltaic panel floorplanning for residential installations.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

All-digital embedded meters for on-line power estimation.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Multiple alignment of packet sequences for efficient communication in a many-core neuromorphic system: work-in-progress.
Proceedings of the International Conference on Compilers, 2018

Impact of graph partitioning on SNN placement for a multi-core neuromorphic architecture: work-in-progress.
Proceedings of the International Conference on Compilers, 2018

Colorectal Cancer Classification using Deep Convolutional Networks - An Experimental Study.
Proceedings of the 11th International Joint Conference on Biomedical Engineering Systems and Technologies (BIOSTEC 2018), 2018

2017
Approximate Energy-Efficient Encoding for Serial Interfaces.
ACM Trans. Design Autom. Electr. Syst., 2017

A Flexible Distributed Infrastructure for Real-Time Cosimulations in Smart Grids.
IEEE Trans. Industrial Informatics, 2017

A Software Toolchain for Variability Awareness on Heterogenous Multicore Platforms.
IEEE Trans. Emerging Topics Comput., 2017

A Layered Methodology for the Simulation of Extra-Functional Properties in Smart Systems.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2017

CONTREX: Design of embedded mixed-criticality CONTRol systems under consideration of EXtra-functional properties.
Microprocessors and Microsystems - Embedded Hardware Design, 2017

Information Modeling for Virtual and Augmented Reality.
IT Professional, 2017

A scalable middleware-based infrastructure for energy management and visualization in city districts.
EAI Endorsed Trans. Cloud Systems, 2017

Optimal content-dependent dynamic brightness scaling for OLED displays.
Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017

A Convolutional Neural Network Fully Implemented on FPGA for Embedded Platforms.
Proceedings of the New Generation of CAS, 2017

An Efficient MPI Implementation for Multi-Coreneuromorphic Platforms.
Proceedings of the New Generation of CAS, 2017

Workload-driven frequency-aware battery sizing.
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017

PVInGrid: A Distributed Infrastructure for Evaluating the Integration of Photovoltaic Systems in Smart Grid.
Proceedings of the Technological Innovation for Smart Systems, 2017

A methodology for the design of dynamic accuracy operators by runtime back bias.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

A circuit-equivalent battery model accounting for the dependency on load frequency.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Building Energy Modelling and Monitoring by Integration of IoT Devices and Building Information Models.
Proceedings of the 41st IEEE Annual Computer Software and Applications Conference, 2017

A Multi-modal Brain Image Registration Framework for US-guided Neuronavigation Systems - Integrating MR and US for Minimally Invasive Neuroimaging.
Proceedings of the 10th International Joint Conference on Biomedical Engineering Systems and Technologies (BIOSTEC 2017), 2017

2016
Distributed Software Infrastructure for General Purpose Services in Smart Grid.
IEEE Trans. Smart Grid, 2016

Quasi-Adiabatic Logic Arrays for Silicon and Beyond-Silicon Energy-Efficient ICs.
IEEE Trans. on Circuits and Systems, 2016

Event-Driven User-Centric Middleware for Energy-Efficient Buildings and Public Spaces.
IEEE Systems Journal, 2016

Logic Synthesis for Silicon and Beyond-Silicon Multi-gate Pass-Logic Circuits.
Proceedings of the VLSI-SoC: System-on-Chip in the Nanoscale Era - Design, Verification and Reliability, 2016

Multi-function logic synthesis of silicon and beyond-silicon ultra-low power pass-gates circuits.
Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016

Beyond Ideal DVFS Through Ultra-Fine Grain Vdd-Hopping.
Proceedings of the VLSI-SoC: System-on-Chip in the Nanoscale Era - Design, Verification and Reliability, 2016

Ultra-Fine Grain Vdd-Hopping for energy-efficient Multi-Processor SoCs.
Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016

Frequency domain characterization of batteries for the design of energy storage subsystems.
Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016

Distributed Software Infrastructure for Evaluating the Integration of Photovoltaic Systems in Urban Districts.
Proceedings of the SMARTGREENS 2016, 2016

A Li-Ion Battery Charge Protocol with Optimal Aging-Quality of Service Trade-off.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016

Enabling quasi-adiabatic logic arrays for silicon and beyond-silicon technologies.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

A Unified Model of Power Sources for the Simulation of Electrical Energy Systems.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

Graphene-PLA (GPLA): a Compact and Ultra-Low Power Logic Array Architecture.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

Approximate Differential Encoding for Energy-Efficient Serial Communication.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

Fast Thermal Simulation using SystemC-AMS.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

Automated 3D immunofluorescence analysis of Dorsal Root Ganglia for the investigation of neural circuit alterations: a preliminary study.
Proceedings of the Position Papers of the 2016 Federated Conference on Computer Science and Information Systems, 2016

IP-XACT for smart systems design: extensions for the integration of functional and extra-functional models.
Proceedings of the 2016 Forum on Specification and Design Languages, 2016

CONTREX: Design of Embedded Mixed-Criticality CONTRol Systems under Consideration of EXtra-Functional Properties.
Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016

Low-overhead adaptive constrast enhancement and power reduction for OLEDs.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Panel: Looking backwards and forwards.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Serial T0: approximate bus encoding for energy-efficient transmission of sensor signals.
Proceedings of the 53rd Annual Design Automation Conference, 2016

2015
A Statistical Model-Based Cell-to-Cell Variability Management of Li-ion Battery Pack.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2015

Ultra-low power circuits using graphene p-n junctions and adiabatic computing.
Microprocessors and Microsystems - Embedded Hardware Design, 2015

Addressing the Smart Systems design challenge: The SMAC platform.
Microprocessors and Microsystems - Embedded Hardware Design, 2015

District Information Modeling and Energy Management.
IT Professional, 2015

Evaluating a Hardware-Based Approach for Detecting Resistive-Open Defects in SRAMs.
Proceedings of the 28th International Conference on VLSI Design, 2015

A Temperature-Aware Battery Cycle Life Model for Different Battery Chemistries.
Proceedings of the VLSI-SoC: Design for Reliability, Security, and Low Power, 2015

An equation-based battery cycle life model for various battery chemistries.
Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015

multiFLEX: Flexible Multi-utility, Multi-service Smart Metering Architecture for Energy Vectors with Active Prosumers.
Proceedings of the SMARTGREENS 2015, 2015

Top-Down Profiling of Application Specific Many-core Neuromorphic Platforms.
Proceedings of the IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2015

An automated design flow for approximate circuits based on reduced precision redundancy.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

An aging-aware battery charge scheme for mobile devices exploiting plug-in time patterns.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Design and Characterization of Analog-to-Digital Converters using Graphene P-N Junctions.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

Exploiting the Expressive Power of Graphene Reconfigurable Gates via Post-Synthesis Optimization.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

Characterizing the Activity Factor in NBTI Aging Models for Embedded Cores.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

A tool-chain to foster a new business model for photovoltaic systems integration exploiting an Energy Community approach.
Proceedings of the 20th IEEE Conference on Emerging Technologies & Factory Automation, 2015

Unsupervised HEp-2 mitosis recognition in indirect immunofluorescence imaging.
Proceedings of the 37th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2015

Enhancing Energy Awareness Through the Analysis of Thermal Energy Consumption.
Proceedings of the Workshops of the EDBT/ICDT 2015 Joint Conference (EDBT/ICDT), 2015

A new distributed framework for integration of district energy data from heterogeneous devices.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

One-pass logic synthesis for graphene-based Pass-XNOR logic circuits.
Proceedings of the 52nd Annual Design Automation Conference, 2015

Energy Signature Analysis: Knowledge at Your Fingertips.
Proceedings of the 2015 IEEE International Congress on Big Data, New York City, NY, USA, June 27, 2015

2014
Energy/Lifetime Cooptimization by Cache Partitioning With Graceful Performance Degradation.
IEEE Trans. VLSI Syst., 2014

Dynamic Indexing: Leakage-Aging Co-Optimization for Caches.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2014

Row-based body-bias assignment for dynamic thermal clock-skew compensation.
Microelectronics Journal, 2014

Modeling of Physical Defects in PN Junction Based Graphene Devices.
J. Electronic Testing, 2014

Message from the program chairs.
Proceedings of the 9th IEEE International Symposium on Industrial Embedded Systems, 2014

A framework for efficient evaluation and comparison of EES Models.
Proceedings of the 24th International Workshop on Power and Timing Modeling, 2014

miR-SEA: miRNA Seed Extension based Aligner Pipeline for NGS Expression Level Extraction.
Proceedings of the International Work-Conference on Bioinformatics and Biomedical Engineering, 2014

An open-source framework for formal specification and simulation of electrical energy systems.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014

A compact macromodel for the charge phase of a battery with typical charging protocol.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014

DIMCloud: A Distributed Framework for District Energy Simulation and Management.
Proceedings of the Internet of Things. User-Centric IoT, 2014

Automated generation of battery aging models from datasheets.
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

Modeling of the charging behavior of li-ion batteries based on manufacturer's data.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

Design and implementation of a multi-standard event-driven energy management system for smart buildings.
Proceedings of the IEEE 3rd Global Conference on Consumer Electronics, 2014

Towards a Software Infrastructure for District Energy Management.
Proceedings of the 12th IEEE International Conference on Embedded and Ubiquitous Computing, 2014

Ultra Low-Power Computation via Graphene-Based Adiabatic Logic Gates.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

Pass-XNOR logic: A new logic style for P-N junction based graphene circuits.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Thermal management of batteries using a hybrid supercapacitor architecture.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Cache aging reduction with improved performance using dynamically re-sizable cache.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

A cross-level verification methodology for digital IPs augmented with embedded timing monitors.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Statistical Battery Models and Variation-Aware Battery Management.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013
Gelsius: A Literature-Based Workflow for Determining Quantitative Associations between Genes and Biological Processes.
IEEE/ACM Trans. Comput. Biology Bioinform., 2013

Layout-Driven Post-Placement Techniques for Temperature Reduction and Thermal Gradient Minimization.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2013

Modeling and characterization of thermally induced skew on clock distribution networks of nanometric ICs.
Microelectronics Journal, 2013

Integration of Literature with Heterogeneous Information for Genes Correlation Scoring.
JETC, 2013

Acceleration of coarse grain molecular dynamics on GPU architectures.
Journal of Computational Chemistry, 2013

A fully standard-cell delay measurement circuit for timing variability detection.
Proceedings of the 2013 23rd International Workshop on Power and Timing Modeling, 2013

A framework with temperature-aware accuracy levels for battery modeling from datasheets.
Proceedings of the 2013 23rd International Workshop on Power and Timing Modeling, 2013

Power modeling and characterization of Graphene-based logic gates.
Proceedings of the 2013 23rd International Workshop on Power and Timing Modeling, 2013

Investigating the behavior of physical defects in pn-junction based reconfigurable graphene devices.
Proceedings of the 14th Latin American Test Workshop, 2013

Technique based on On-Chip Current Sensors and Neighbourhood Comparison Logic to detect resistive-open defects in SRAMs.
Proceedings of the 14th Latin American Test Workshop, 2013

A statistical model of cell-to-cell variation in Li-ion batteries for system-level design.
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

An automated framework for generating variable-accuracy battery models from datasheet information.
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

Exploration of different implementation styles for graphene-based reconfigurable gates.
Proceedings of 2013 International Conference on IC Design & Technology, 2013

Delay model for reconfigurable logic gates based on graphene PN-junctions.
Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

SMAC: Smart Systems Co-design.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

A verilog-a model for reconfigurable logic gates based on graphene pn-junctions.
Proceedings of the Design, Automation and Test in Europe, 2013

HW-SW integration for energy-efficient/variability-aware computing.
Proceedings of the Design, Automation and Test in Europe, 2013

Energy-optimal SRAM supply voltage scheduling under lifetime and error constraints.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

A Novel Pipeline for V(D)J Junction Identification using RNA-Seq Paired-end Reads.
Proceedings of the BIOINFORMATICS 2013 - Proceedings of the International Conference on Bioinformatics Models, Methods and Algorithms, Barcelona, Spain, 11, 2013

Classification of HEp-2 Staining Patterns in ImmunoFluorescence Images - Comparison of Support Vector Machines and Subclass Discriminant Analysis Strategies.
Proceedings of the BIOINFORMATICS 2013 - Proceedings of the International Conference on Bioinformatics Models, Methods and Algorithms, Barcelona, Spain, 11, 2013

2012
Design Techniques for NBTI-Tolerant Power-Gating Architectures.
IEEE Trans. on Circuits and Systems, 2012

Design Techniques and Architectures for Low-Leakage SRAMs.
IEEE Trans. on Circuits and Systems, 2012

On-chip process variation-tracking through an all-digital monitoring architecture.
IET Circuits, Devices & Systems, 2012

Computer-aided techniques for chromogenic immunohistochemistry: Status and directions.
Comp. in Bio. and Med., 2012

Bellerophontes: an RNA-Seq data analysis framework for chimeric transcripts discovery based on accurate fusion model.
Bioinformatics, 2012

Aging-aware caches with graceful degradation of performance.
Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012

On-Chip NBTI and PBTI Tracking through an All-Digital Aging Monitor Architecture.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2012

Energy-optimal caches with guaranteed lifetime.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012

Applying textural features to the classification of HEp-2 cell patterns in IIF images.
Proceedings of the 21st International Conference on Pattern Recognition, 2012

NBTI effects on tree-like clock distribution networks.
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

Investigating the effects of Inverted Temperature Dependence (ITD) on clock distribution networks.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Middleware services for network interoperability in smart energy efficient buildings.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

IR-drop analysis of graphene-based power distribution networks.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Application-specific memory partitioning for joint energy and lifetime optimization.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Characterization of Coarse Grain Molecular Dynamic Simulation Performance on Graphic Processing Unit Architectures.
Proceedings of the BIOINFORMATICS 2012 - Proceedings of the International Conference on Bioinformatics Models, Methods and Algorithms, Vilamoura, Algarve, Portugal, 1, 2012

A Novel Analysis Flow for Fused Transcripts Discovery from Paired-end RNA-Seq Data.
Proceedings of the BIOINFORMATICS 2012 - Proceedings of the International Conference on Bioinformatics Models, Methods and Algorithms, Vilamoura, Algarve, Portugal, 1, 2012

2011
Row-Based Power-Gating: A Novel Sleep Transistor Insertion Methodology for Leakage Power Optimization in Nanometer CMOS Circuits.
IEEE Trans. VLSI Syst., 2011

Fast Computation of Discharge Current Upper Bounds for Clustered Power Gating.
IEEE Trans. VLSI Syst., 2011

Automated Segmentation of Cells With IHC Membrane Staining.
IEEE Trans. Biomed. Engineering, 2011

A Multi-Processing Systems-on-Chip Native Simulation Framework for Power and Thermal-Aware Design.
J. Low Power Electronics, 2011

Power Efficient Variability Compensation Through Clustered Tunable Power-Gating.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2011

Guest Editorial Advances in Design of Energy-Efficient Circuits and Systems (Second Issue).
IEEE J. Emerg. Sel. Topics Circuits Syst., 2011

miREE: miRNA Recognition Elements Ensemble.
BMC Bioinformatics, 2011

Sub-Row Sleep Transistor Insertion for Concurrent Clock-Gating and Power-Gating.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2011

An On-Chip All-Digital PV-Monitoring Architecture for Digital IPs.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2011

Buffering of frequent accesses for reduced cache aging.
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

Partitioned cache architectures for reduced NBTI-induced aging.
Proceedings of the Design, Automation and Test in Europe, 2011

Binding Free Energy Calculation via Molecular Dynamics Simulations for a miRNA: mRNA Interaction.
Proceedings of the BIOINFORMATICS 2011, 2011

Improving Latent Semantic Analysis of Biomedical Literature Integrating UMLS Metathesaurus and Biomedical Pathways Databases.
Proceedings of the Biomedical Engineering Systems and Technologies, 2011

A New Latent Semantic Analysis based Methodology for Knowledge Extraction from Biomedical Literature and Biological Pathways Databases.
Proceedings of the BIOINFORMATICS 2011, 2011

Motion Artifact Correction in ASL images: An Improved Automated Procedure.
Proceedings of the IEEE International Conference on Bioinformatics and Biomedicine, 2011

A novel framework for chimeric transcript detection based on accurate gene fusion model.
Proceedings of the 2011 IEEE International Conference on Bioinformatics and Biomedicine Workshops, 2011

2010
Temperature-Insensitive Dual- Vth Synthesis for Nanometer CMOS Technologies Under Inverse Temperature Dependence.
IEEE Trans. VLSI Syst., 2010

NBTI-Aware Clustered Power Gating.
ACM Trans. Design Autom. Electr. Syst., 2010

Thermal-Aware Clock Tree Design to Increase Timing Reliability of Embedded SoCs.
IEEE Trans. on Circuits and Systems, 2010

Architectural Leakage Power Minimization of Scratchpad Memories by Application-Driven Subbanking.
IEEE Trans. Computers, 2010

Dual-Vt assignment policies in ITD-aware synthesis.
Microelectronics Journal, 2010

A Refinement Methodology for Clock Gating Optimization at Layout Level in Digital Circuits.
J. Low Power Electronics, 2010

Automated segmentation of tissue images for computerized IHC analysis.
Computer Methods and Programs in Biomedicine, 2010

Achieving the way for automated segmentation of nuclei in cancer tissue images through morphology-based approach: A quantitative evaluation.
Comp. Med. Imag. and Graph., 2010

Power-aware partitioning of data converters.
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010

Generating power-hungry test programs for power-aware validation of pipelined processors.
Proceedings of the 23rd Annual Symposium on Integrated Circuits and Systems Design, 2010

Adaptive Task Migration Policies for Thermal Control in MPSoCs.
Proceedings of the VLSI 2010 Annual Symposium - Selected papers, 2010

Adaptive Task Migration Policies for Thermal Control in MPSoCs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

Dynamic indexing: concurrent leakage and aging optimization for caches.
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

Analysis of NBTI-induced SNM degradation in power-gated SRAM cells.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Thermal-aware floorplanning exploration for 3D multi-core architectures.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

Aging effects of leakage optimizations for caches.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

An integrated thermal estimation framework for industrial embedded platforms.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

Post-placement temperature reduction techniques.
Proceedings of the Design, Automation and Test in Europe, 2010

Panel: First commandment at least, do nothing well!
Proceedings of the Design, Automation and Test in Europe, 2010

MicroRNA Target Prediction and Exploration through Candidate Binding Sites Generation.
Proceedings of the CISIS 2010, 2010

An Automated Tool for Scoring Biomedical Terms Correlation Based on Semantic Analysis.
Proceedings of the CISIS 2010, 2010

2009
Design of a Flexible Reactivation Cell for Safe Power-Mode Transition in Power-Gated Circuits.
IEEE Trans. on Circuits and Systems, 2009

Editorial.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2009

Exploiting Temporal Discharge Current Information to Improve the Efficiency of Clustered Power-Gating.
J. Low Power Electronics, 2009

Enhanced switching activity balancing encoding schemes for uniform temperature distribution in on-chip buses.
J. Embedded Computing, 2009

Reducing Timing Overhead in Simultaneously Clock-Gated and Power-Gated Designs by Placement-Aware Clustering.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009

On-chip Thermal Modeling Based on SPICE Simulation.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009

Data-Driven Clock Gating for Digital Filters.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009

NBTI-aware power gating for concurrent leakage and aging optimization.
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009

Placement-aware Clustering for Integrated Clock and Power Gating.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Using soft-edge flip-flops to compensate NBTI-induced delay degradation.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

NBTI-aware sleep transistor design for reliable power-gating.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

Physically clustered forward body biasing for variability compensation in nanometer CMOS design.
Proceedings of the Design, Automation and Test in Europe, 2009

Enabling concurrent clock and power gating in an industrial design flow.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
Dynamic Thermal Clock Skew Compensation Using Tunable Delay Buffers.
IEEE Trans. VLSI Syst., 2008

Editorial.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2008

Thermal-Aware Design Techniques for Nanometer CMOS Circuits.
J. Low Power Electronics, 2008

Implementation of a thermal management unit for canceling temperature-dependent clock skew variations.
Integration, 2008

Joint co-clustering: Co-clustering of genomic and clinical bioimaging data.
Computers & Mathematics with Applications, 2008

Temporal Discharge Current Driven Clustering for Improved Leakage Power Reduction in Row-Based Power-Gating.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008

Multiple power-gating domain (multi-VGND) architecture for improved leakage power reduction.
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008

Reducing leakage power by accounting for temperature inversion dependence in dual-Vt synthesized circuits.
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008

On quantifying the figures of merit of power-gating for leakage power minimization in nanometer CMOS circuits.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Optimal sleep transistor synthesis under timing and area constraints.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

Energy efficiency bounds of pulse-encoded buses.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

Temperature-insensitive synthesis using multi-vt libraries.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

Integrating Clock Gating and Power Gating for Combined Dynamic and Leakage Power Optimization in Digital CMOS Circuits.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

Process Variation Tolerant Pipeline Design Through a Placement-Aware Multiple Voltage Island Design Style.
Proceedings of the Design, Automation and Test in Europe, 2008

A Scalable Algorithmic Framework for Row-Based Power-Gating.
Proceedings of the Design, Automation and Test in Europe, 2008

Optimal MTCMOS Reactivation Under Power Supply Noise and Performance Constraints.
Proceedings of the Design, Automation and Test in Europe, 2008

Automated Discrimination of Pathological Regions in Tissue Images: Unsupervised Clustering vs. Supervised SVM Classification.
Proceedings of the Biomedical Engineering Systems and Technologies, 2008

Fully-Automated Segmentation of Tumor Areas in Tissue Confocal Images - Comparison between a Custom Unsupervised and a Supervised SVM Approach.
Proceedings of the First International Conference on Biomedical Electronics and Devices, 2008

Segmentation of nuclei in cancer tissue images: Contrasting active contours with morphology-based approach.
Proceedings of the 8th IEEE International Conference on Bioinformatics and Bioengineering, 2008

2007
In Memoriam: Margarida F. Jacome.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

Editorial.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

New Adaptive Encoding Schemes for Switching Activity Balancing in On-Chip Buses.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007

Timing-driven row-based power gating.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

Power-optimal RTL arithmetic unit soft-macro selection strategy for leakage-sensitive technologies.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

Locality-driven architectural cache sub-banking for leakage energy reduction.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

Design Exploration of a Thermal Management Unit for Dynamic Control of Temperature-Induced Clock Skew.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

Interactive presentation: Efficient computation of discharge current upper bounds for clustered sleep transistor sizing.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Architectural leakage-aware management of partitioned scratchpad memories.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Early Power-Aware Design & Validation: Myth or Reality?
Proceedings of the 44th Design Automation Conference, 2007

Selection of Tumor Areas and Segmentation of Nuclear Membranes in Tissue Confocal Images: A Fully Automated Approach.
Proceedings of the IEEE International Conference on Bioinformatics and Biomedicine, 2007

Gene-Markers Representation for Microarray Data Integration.
Proceedings of the 7th IEEE International Conference on Bioinformatics and Bioengineering, 2007

2006
Low-energy RGB color approximation for digital LCD interfaces.
IEEE Trans. Consumer Electronics, 2006

Reducing Conflict Misses by Application-Specific Reconfigurable Indexing.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

TOM: a web-based integrated approach for identification of candidate disease genes.
Nucleic Acids Research, 2006

Energy-Efficient Value Based Selective Refresh for Embedded DRAMS.
J. Low Power Electronics, 2006

Implementation Strategy and Results of an Energy-Aware System-on-Chip for 5 GHz WLAN Applications.
J. Low Power Electronics, 2006

Optimized Technique for Dna Structural Properties Discovering.
International Journal on Artificial Intelligence Tools, 2006

Dynamic Management of Thermally-Induced Clock Skew: An Implementation Perspective.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

Dynamic thermal clock skew compensation using tunable delay buffers.
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006

Mining Gene Sets for Measuring Similarities.
Proceedings of the 11th IEEE Symposium on Computers and Communications (ISCC 2006), 2006

Low-energy pixel approximation for DVI-based LCD interfaces.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Implications of ultra low-voltage devices on design techniques for controlling leakage in NanoCMOS circuits.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

STV-Cache: a leakage energy-efficient architecture for data caches.
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

Low-power design tools: are EDA vendors taking this matter seriously?
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Thermal resilient bounded-skew clock tree optimization methodology.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Enabling fine-grain leakage management by voltage anchor insertion.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Computer-Aided Evaluation of Protein Expression in Pathological Tissue Images.
Proceedings of the 19th IEEE International Symposium on Computer-Based Medical Systems (CBMS 2006), 2006

2005
Automated DNA fragments recognition and sizing through AFM image processing.
IEEE Trans. Information Technology in Biomedicine, 2005

Energy-efficient bus encoding for LCD digital display interfaces.
IEEE Trans. Consumer Electronics, 2005

A scalable algorithm for RTL insertion of gated clocks based on ODCs computation.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2005

Automatic intrinsic DNA curvature computation from AFM images.
IEEE Trans. Biomed. Engineering, 2005

Design and Implementation of a Memory Generator for Low-Energy Application-Specific Block-Enabled SRAMs.
Proceedings of the Integrated Circuit and System Design, 2005

Energy-Efficient Value-Based Selective Refresh for Embedded DRAMs.
Proceedings of the Integrated Circuit and System Design, 2005

Exploiting Cross-Channel Correlation for Energy-Efficient LCD Bus Encoding.
Proceedings of the Integrated Circuit and System Design, 2005

Energy-Aware System-on-Chip for 5 GHz Wireless LANs.
Proceedings of the Integrated Circuit and System Design, 2005

Frame Buffer Energy Optimization by Pixel Prediction.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Energy-Efficient Color Approximation for Digital LCD Interfaces.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Exploring the impact of architectural parameters on energy efficiency of application-specific block-enabled SRAMs.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

Zero clustering: an approach to extend zero compression to instruction caches.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

Low-overhead state-retaining elements for low-leakage MTCMOS design.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

2004
Memory energy minimization by data compression: algorithms, architectures and implementation.
IEEE Trans. VLSI Syst., 2004

Leakage power optimization in standard-cell designs.
Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, 2004

RTL power estimation and optimization.
Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, 2004

A Low-Power Encoding Scheme for GigaByte Video Interfaces.
Proceedings of the Integrated Circuit and System Design, 2004

Power-aware clock tree planning.
Proceedings of the 2004 International Symposium on Physical Design, 2004

Limited intra-word transition codes: an energy-efficient bus encoding for LCD display interfaces.
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004

Post-layout leakage power minimization based on distributed sleep transistor insertion.
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004

Crosstalk energy reduction by temporal shielding.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Energy-performance tradeoffs for the shared memory in multi-processor systems-on-chip.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Reducing cache misses by application-specific re-configurable indexing.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Energy-efficient bus encoding for LCD displays.
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

Synthesis of Partitioned Shared Memory Architectures for Energy-Efficient Multi-Processor SoC.
Proceedings of the 2004 Design, 2004

Block-Enabled Memory Macros: Design Space Exploration and Application-Specific Tuning.
Proceedings of the 2004 Design, 2004

Sizing and Characterization of Leakage-Control Cells for Layout-Aware Distributed Power-Gating.
Proceedings of the 2004 Design, 2004

A Scalable ODC-Based Algorithm for RTL Insertion of Gated Clocks.
Proceedings of the 2004 Design, 2004

Techniques for Enhancing Computation of DNA Curvature Molecules.
Proceedings of the 4th IEEE International Symposium on BioInformatics and BioEngineering (BIBE 2004), 2004

2003
Scheduling battery usage in mobile systems.
IEEE Trans. VLSI Syst., 2003

Discharge Current Steering for Battery Lifetime Optimization.
IEEE Trans. Computers, 2003

Statistical Power Estimation of Behavioral Descriptions.
Proceedings of the Integrated Circuit and System Design, 2003

Hardw are Implementation of Data Compression Algorithms for Memory Energy Optimization.
Proceedings of the 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), 2003

Energy-efficient data scrambling on memory-processor interfaces.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

Increasing the locality of memory access patterns by low-overhead hardware address relocation.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Combining wire swapping and spacing for low-power deep-submicron buses.
Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003

A novel architecture for power maskable arithmetic units.
Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003

Improving the Efficiency of Memory Partitioning by Address Clustering.
Proceedings of the 2003 Design, 2003

A New Algorithm for Energy-Driven Data Compression in VLIW Embedded Processors.
Proceedings of the 2003 Design, 2003

Clock-tree power optimization based on RTL clock-gating.
Proceedings of the 40th Design Automation Conference, 2003

Energy-aware design techniques for differential power analysis protection.
Proceedings of the 40th Design Automation Conference, 2003

2002
Guest editorial: low-power electronics and design.
IEEE Trans. VLSI Syst., 2002

Minimizing memory access energy in embedded systems by selective instruction compression.
IEEE Trans. VLSI Syst., 2002

Offline Data Profiling Techniques to Enhance Memory Compression in Embedded Systems.
Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002

Discharge current steering for battery lifetime optimization.
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

An adaptive data compression scheme for memory traffic minimization in processor-based systems.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Enhanced clustered voltage scaling for low power.
Proceedings of the 12th ACM Great Lakes Symposium on VLSI 2002, 2002

Wire Placement for Crosstalk Energy Minimization in Address Buses.
Proceedings of the 2002 Design, 2002

Hardware-Assisted Data Compression for Energy Minimization in Systems with Embedded Processors.
Proceedings of the 2002 Design, 2002

2001
Stream synthesis for efficient power simulation based on spectral transforms.
IEEE Trans. VLSI Syst., 2001

Estimation of lower and upper bounds on the power consumption from scheduled data flow graphs.
IEEE Trans. VLSI Syst., 2001

Parameterized RTL power models for soft macros.
IEEE Trans. VLSI Syst., 2001

Discrete-time battery models for system-level low-power design.
IEEE Trans. VLSI Syst., 2001

Synthesis of power-managed sequential components based oncomputational kernel extraction.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2001

Guest Editor's Introduction: Dynamic Power Management of Electronic Systems.
IEEE Design & Test of Computers, 2001

Low-energy for deep-submicron address buses.
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

On-the-fly layout generation for PTL macrocells.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

Extending lifetime of portable systems by battery scheduling.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

From Architecture to Layout: Partitioned Memory Synthesis for Embedded Systems-on-Chip.
Proceedings of the 38th Design Automation Conference, 2001

2000
Glitch power minimization by selective gate freezing.
IEEE Trans. VLSI Syst., 2000

Power optimization of technology-dependent circuits based on symbolic computation of logic implications.
ACM Trans. Design Autom. Electr. Syst., 2000

Symbolic optimization of interacting controllers based onredundancy identification and removal.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2000

A multilevel engine for fast power simulation of realistic inputstreams.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2000

Increasing Energy Efficiency of Embedded Systems by Application-Specific Memory Hierarchy Generation.
IEEE Design & Test of Computers, 2000

Power Models for Semi-autonomous RTL Macros.
Proceedings of the Integrated Circuit Design, 2000

RTL Estimation of Steering Logic Power.
Proceedings of the Integrated Circuit Design, 2000

Battery-Driven Dynamic Power Management of Portable Systems.
Proceedings of the 13th International Symposium on System Synthesis, 2000

Power Macromodeling for a High Quality RT-Level Power Estimation.
Proceedings of the 1st International Symposium on Quality of Electronic Design (ISQED 2000), 2000

Supporting system-level power exploration for DSP applications.
Proceedings of the 10th ACM Great Lakes Symposium on VLSI 2000, 2000

Regression-based RTL power models for controllers.
Proceedings of the 10th ACM Great Lakes Symposium on VLSI 2000, 2000

A Discrete-Time Battery Model for High-Level Power Estimation.
Proceedings of the 2000 Design, 2000

Synthesis of application-specific memories for power optimization in embedded systems.
Proceedings of the 37th Conference on Design Automation, 2000

1999
Symbolic synthesis of clock-gating logic for power optimization of synchronous controllers.
ACM Trans. Design Autom. Electr. Syst., 1999

Automatic Synthesis of Large Telescopic Units Based on Near-Minimum Timed Supersetting.
IEEE Trans. Computers, 1999

Selective instruction compression for memory energy reduction in embedded systems.
Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999

Parameterized RTL power models for combinational soft macros.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

Regression-Based Macromodeling for Delay Estimation of Behavioral Components.
Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999

Clustered Table-Based Macromodels for RTL Power Estimation.
Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999

Region Compression: A New Scheme for Memory Energy Minimization in Embedded Systems.
Proceedings of the 25th EUROMICRO '99 Conference, 1999

Glitch Power Minimization by Gate Freezing.
Proceedings of the 1999 Design, 1999

Synthesis of Low-Overhead Interfaces for Power-Efficient Communication over Wide Buses.
Proceedings of the 36th Conference on Design Automation, 1999

Kernel-Based Power Optimization of RTL Components: Exact and Approximate Extraction Algorithms.
Proceedings of the 36th Conference on Design Automation, 1999

1998
Power optimization of core-based systems by address bus encoding.
IEEE Trans. VLSI Syst., 1998

High-level power modeling, estimation, and optimization.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1998

Telescopic units: a new paradigm for performance optimization of VLSI designs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1998

Stream synthesis for efficient power simulation based on spectral transforms.
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998

Symbolic algorithms for layout-oriented synthesis of pass transistor logic circuits.
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

Reducing Power Consumption of Dedicated Processors Through Instruction Set Encoding.
Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998

Timed Supersetting and the Synthesis of Telescopic Units.
Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998

Power Estimation of Behavioral Descriptions.
Proceedings of the 1998 Design, 1998

Address Bus Encoding Techniques for System-Level Power Optimization.
Proceedings of the 1998 Design, 1998

In-Place Power Optimization for LUT-Based FPGAs.
Proceedings of the 35th Conference on Design Automation, 1998

Computational Kernels and their Application to Sequential Power Optimization.
Proceedings of the 35th Conference on Design Automation, 1998

1997
Formal verification of digital systems by automatic reduction of data paths.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1997

Symbolic timing analysis and resynthesis for low power of combinational circuits containing false paths.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1997

Algebraic Decision Diagrams and Their Applications.
Formal Methods in System Design, 1997

Testing Core-Based Systems: A Symbolic Methodology.
IEEE Design & Test of Computers, 1997

System-level power optimization of special purpose applications: the beach solution.
Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997

Fast power estimation for deterministic input streams.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

Accurate Entropy Calculation for Large Logic Circuits Based on Output Clustering.
Proceedings of the 7th Great Lakes Symposium on VLSI (GLS-VLSI '97), 1997

Asymptotic Zero-Transition Activity Encoding for Address Busses in Low-Power Microprocessor-Based Systems.
Proceedings of the 7th Great Lakes Symposium on VLSI (GLS-VLSI '97), 1997

Symbolic synthesis of clock-gating logic for power optimization of control-oriented synchronous networks.
Proceedings of the European Design and Test Conference, 1997

High-Level Power Modeling, Estimation, and Optimization.
Proceedings of the 34st Conference on Design Automation, 1997

Telescopic Units: Increasing the Average Throughput of Pipelined Designs by Adaptive Latency Control.
Proceedings of the 34st Conference on Design Automation, 1997

1996
Markovian analysis of large finite state machines.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1996

Algorithms for approximate FSM traversal based on state space decomposition.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1996

Automatic state space decomposition for approximate FSM traversal based on circuit analysis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1996

Symbolic computation of logic implications for technology-dependent low-power synthesis.
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996

Enhancing FSM Traversal by Temporary Re-Encoding.
Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996

Exact Computation of the Entropy of a Logic Circuit.
Proceedings of the 6th Great Lakes Symposium on VLSI (GLS-VLSI '96), 1996

Test Generation for Networks of Interacting FSMs Using Symbolic Techniques.
Proceedings of the 6th Great Lakes Symposium on VLSI (GLS-VLSI '96), 1996

BDD-based testability estimation of VHDL designs.
Proceedings of the conference on European design automation, 1996

Symbolic Optimization of FSM Networks Based on Sequential ATPG Techniques.
Proceedings of the 33st Conference on Design Automation, 1996

1995
Using connectivity and spectral methods to characterize the structure of sequential logic circuits.
Microprocessing and Microprogramming, 1995

Using symbolic Rademacher-Walsh spectral transforms to evaluate the correlation between Boolean functions.
Proceedings of the 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), 1995

Estimating worst-case power consumption of CMOS circuits modeled as symbolic neural networks.
Proceedings of the 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), 1995

Predicting the functional complexity of combinational circuits by symbolic spectral analysis of Boolean functions.
Proceedings of the Proceedings EURO-DAC'95, 1995

Computing the Maximum Power Cycles of a Sequential Circuit.
Proceedings of the 32st Conference on Design Automation, 1995

1994
A test generation program for sequential circuits.
J. Electronic Testing, 1994

A Structural Approach to State Space Decomposition for Approximate Reachability Analysis.
Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

A symbolic method to reduce power consumption of circuits containing false paths.
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

Symbolic Algorithms to Calculate Steady-State Probabilities of a Finite State Machine.
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

A State Space Decomposition Algorithm for Approximate FSM Traversal.
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

Timing Analysis of Combinational Circuits using ADD's.
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

Probabilistic Analysis of Large Finite State Machines.
Proceedings of the 31st Conference on Design Automation, 1994

1993
Algebraic decision diagrams and their applications.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

Modeling stuck-open faults in CMOS iterative circuits.
Proceedings of the Third Great Lakes Symposium on Design Automation of High Performance VLSI Systems, 1993

Δ-trees of a graph: introduction and formal definition.
Proceedings of the Third Great Lakes Symposium on Design Automation of High Performance VLSI Systems, 1993

Algorithms for Approximate FSM Traversal.
Proceedings of the 30th Design Automation Conference. Dallas, 1993

1992
Techniques to increase sequential ATPG performance.
Proceedings of the 10th IEEE VLSI Test Symposium (VTS'92), 1992

Verification of systems containing counters.
Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

1991
An algebraic approach to test generation for sequential circuits.
Proceedings of the First Great Lakes Symposium on VLSI, 1991


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