Elham Safi

According to our database, Elham Safi authored at least 9 papers between 2003 and 2011.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2011

Two-Stage, Pipelined Register Renaming.

Elham Safi, Andreas Moshovos, Andreas G. Veneris

IEEE Trans. Very Large Scale Integr. Syst., 2011

2010

On the Latency and Energy of Checkpointed Superscalar Register Alias Tables.

Elham Safi, Andreas Moshovos, Andreas G. Veneris

IEEE Trans. Very Large Scale Integr. Syst., 2010

2009

A physical-level study of the compacted matrix instruction scheduler for dynamically-scheduled superscalar processors.

Elham Safi, Andreas Moshovos, Andreas G. Veneris

Proceedings of the 2009 International Conference on Embedded Computer Systems: Architectures, 2009

2008

A physical level study and optimization of CAM-based checkpointed register alias table.

Elham Safi, Andreas Moshovos, Andreas G. Veneris

Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008

2007

A Framework for Coarse-Grain Optimizations in the On-Chip Memory Hierarchy.

Jason Zebchuk, Elham Safi, Andreas Moshovos

Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-40 2007), 2007

On the latency, energy and area of checkpointed, superscalar register alias tables.

Elham Safi, Patrick Akl, Andreas Moshovos, Andreas G. Veneris, Aggeliki Arapoyanni

Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

2006

L-CBF: a low-power, fast counting bloom filter architecture.

Elham Safi, Andreas Moshovos, Andreas G. Veneris

Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006

2003

Processor Testing Using an ADL Description and Genetic Algorithms.

Elham Safi, Reihaneh Saberi, Zohreh Karimi, Zainalabedin Navabi

Proceedings of the IFIP VLSI-SoC 2003, 2003

Utilizing Various ADL Facets for Instruction Level CPU Test.

Elham Safi, Zohreh Karimi, Maghsoud Abbaspour, Zainalabedin Navabi

Proceedings of the Fourth International Workshop on Microprocessor Test and Verification, 2003