Andreas G. Veneris

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017

Leveraging Software Configuration Management in Automated RTL Design Debug.

[BibT_eX]

[DOI]

IEEE Des. Test, 2017

Learning lemma support graphs in Quip and IC3.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2nd International Verification and Security Workshop, 2017

Fast GPU-Based Influence Maximization Within Finite Deadlines via Node-Level Parallelism.

[BibT_eX]

[DOI]

Proceedings of the Advances in Data Mining. Applications and Theoretical Aspects, 2017

Learning support sets in IC3 and Quip: The good, the bad, and the ugly.

[BibT_eX]

[DOI]

Proceedings of the 2017 Formal Methods in Computer Aided Design, 2017

An extensible perceptron framework for revision RTL debug automation.

[BibT_eX]

[DOI]

Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016

Exemplar-based Failure Triage for Regression Design Debugging.

[BibT_eX]

[DOI]

J. Electron. Test., 2016

On simulation-based metrics that characterize the behavior of RTL errors.

[BibT_eX]

[DOI]

Proceedings of the Summer Computer Simulation Conference, 2016

Revision debug with non-linear version history in regression verification.

[BibT_eX]

[DOI]

Proceedings of the 1st IEEE International Verification and Security Workshop, 2016

Efficient Selection of Suspect Sets in Unreachable State Diagnosis.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Artificial Intelligence and Mathematics, 2016

Root-cause analysis for memory-locked errors.

[BibT_eX]

[DOI]

Djordje Maksimovic

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

A complete approach to unreachable state diagnosability via property directed reachability.

[BibT_eX]

[DOI]

Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015

Constructing stability-based clock gating with hierarchical clustering.

[BibT_eX]

[DOI]

Proceedings of the 25th International Workshop on Power and Timing Modeling, 2015

Mining simulation metrics for failure triage in regression testing.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015

Clustering-based revision debug in regression verification.

[BibT_eX]

[DOI]

Djordje Maksimovic

Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

FudgeFactor: Syntax-Guided Synthesis for Accurate RTL Error Localization and Correction.

[BibT_eX]

[DOI]

Proceedings of the Hardware and Software: Verification and Testing, 2015

Automated rectification methodologies to functional state-space unreachability.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014

Debugging RTL Using Structural Dominance.

[BibT_eX]

[DOI]

Bao Le

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Clustering-based failure triage for RTL regression debugging.

[BibT_eX]

[DOI]

Proceedings of the 2014 International Test Conference, 2014

Simulation and satisfiability guided counter-example triage for RTL design debugging.

[BibT_eX]

[DOI]

Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

Multiple clock domain synchronization in a QBF-based verification environment.

[BibT_eX]

[DOI]

Djordje Maksimovic

Bao Le

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

Automated debugging of missing assumptions.

[BibT_eX]

[DOI]

Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013

Path-Directed Abstraction and Refinement for SAT-Based Design Debugging.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Early detection of current hot spots in power gated designs.

[BibT_eX]

[DOI]

Dipanjan Sengupta

Erhan Ergin

Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

A failure triage engine based on error trace signature extraction.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013

Accelerating post silicon debug of deep electrical faults.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013

Reviving erroneous stability-based clock-gating using partial Max-SAT.

[BibT_eX]

[DOI]

Bao Le

Dipanjan Sengupta

Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012

Automating Data Analysis and Acquisition Setup in a Silicon Debug Environment.

[BibT_eX]

[DOI]

Nicola Nicolici

IEEE Trans. Very Large Scale Integr. Syst., 2012

Maximum Circuit Activity Estimation Using Pseudo-Boolean Satisfiability.

[BibT_eX]

[DOI]

Farid N. Najm

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Multi-objective voltage island floorplanning using sequence pair representation.

[BibT_eX]

[DOI]

Sustain. Comput. Informatics Syst., 2012

Lazy suspect-set computation: fault diagnosis for deep electrical bugs.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

Automated debugging of missing input constraints in a formal verification environment.

[BibT_eX]

[DOI]

Proceedings of the Formal Methods in Computer-Aided Design, 2012

Leveraging reconfigurability to raise productivity in FPGA functional debug.

[BibT_eX]

[DOI]

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Non-solution implications using reverse domination in a modern SAT-based debugging environment.

[BibT_eX]

[DOI]

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Automated data analysis techniques for a modern silicon debug environment.

[BibT_eX]

[DOI]

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

On error tolerance and Engineering Change with Partially Programmable Circuits.

[BibT_eX]

[DOI]

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011

Two-Stage, Pipelined Register Renaming.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2011

Automating Logic Transformations With Approximate SPFDs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Debugging with dominance: On-the-fly RTL debug solution implications.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Sequence pair based voltage island floorplanning.

[BibT_eX]

[DOI]

Proceedings of the 2011 International Green Computing Conference and Workshops, 2011

Automated debugging of SystemVerilog assertions.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2011

From RTL to silicon: The case for automated debug.

[BibT_eX]

[DOI]

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

Managing complexity in design debugging with sequential abstraction and refinement.

[BibT_eX]

[DOI]

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010

On the Latency and Energy of Checkpointed Superscalar Register Alias Tables.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2010

Bounded Model Debugging.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Automated Design Debugging With Maximum Satisfiability.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Robust QBF Encodings for Sequential Circuits with Applications to Verification, Debug, and Test.

[BibT_eX]

[DOI]

Marco Benedetti

IEEE Trans. Computers, 2010

An Automated Framework for Correction and Debug of PSL Assertions.

[BibT_eX]

[DOI]

Proceedings of the 11th International Workshop on Microprocessor Test and Verification, 2010

Automated silicon debug data analysis techniques for a hardware data acquisition environment.

[BibT_eX]

[DOI]

Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Leveraging dominators for preprocessing QBF.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

Managing verification error traces with bounded model debugging.

[BibT_eX]

[DOI]

Farid N. Najm

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009

Automated Design Debugging With Abstraction and Refinement.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

A physical-level study of the compacted matrix instruction scheduler for dynamically-scheduled superscalar processors.

[BibT_eX]

[DOI]

Proceedings of the 2009 International Conference on Embedded Computer Systems: Architectures, 2009

Automated debugging with high level abstraction and refinement.

[BibT_eX]

[DOI]

Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2009

Spatial and temporal design debug using partial MaxSAT.

[BibT_eX]

[DOI]

Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

Scaling VLSI design debugging with interpolation.

[BibT_eX]

[DOI]

Proceedings of 9th International Conference on Formal Methods in Computer-Aided Design, 2009

Sequential logic rectifications with approximate SPFDs.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2009

Automated data analysis solutions to silicon debug.

[BibT_eX]

[DOI]

Nicola Nicolici

Proceedings of the Design, Automation and Test in Europe, 2009

The day Sherlock Holmes decided to do EDA.

[BibT_eX]

[DOI]

Proceedings of the 46th Design Automation Conference, 2009

2008

L-CBF: A Low-Power, Fast Counting Bloom Filter Architecture.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2008

Improved SAT-based Reachability Analysis with Observability Don't Cares.

[BibT_eX]

[DOI]

Rolf Drechsler

J. Satisf. Boolean Model. Comput., 2008

A physical level study and optimization of CAM-based checkpointed register alias table.

[BibT_eX]

[DOI]

Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008

On the Minimization of Potential Transient Errors and SER in Logic Circuits Using SPFD.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008

A succinct memory model for automated design debugging.

[BibT_eX]

[DOI]

Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

2007

On the latency, energy and area of checkpointed, superscalar register alias tables.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

A performance-driven QBF-based iterative logic array representation with applications to verification, debug and test.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Improved Design Debugging Using Maximum Satisfiability.

[BibT_eX]

[DOI]

Proceedings of the Formal Methods in Computer-Aided Design, 7th International Conference, 2007

Maximum circuit activity estimation using pseudo-boolean satisfiability.

[BibT_eX]

[DOI]

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Automating Logic Rectification by Approximate SPFDs.

[BibT_eX]

[DOI]

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

Trace Compaction using SAT-based Reachability Analysis.

[BibT_eX]

[DOI]

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006

Extraction error modeling and automated model debugging in high-performance custom designs.

[BibT_eX]

[DOI]

Paul J. Thadikaran

Srikanth Venkataraman

IEEE Trans. Very Large Scale Integr. Syst., 2006

Session Abstract.

[BibT_eX]

[DOI]

Yiorgos Makris

Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

Abstraction and Refinement Techniques in Automated Design Debugging.

[BibT_eX]

[DOI]

Proceedings of the Seventh International Workshop on Microprocessor Test and Verification (MTV 2006), 2006

Seamless Integration of SER in Rewiring-Based Design Space Exploration.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International Test Conference, 2006

Integrating observability don't cares in all-solution SAT solvers.

[BibT_eX]

[DOI]

Rolf Drechsler

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

On the relation between simulation-based and SAT-based diagnosis.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Efficient SAT-based Boolean matching for FPGA technology mapping.

[BibT_eX]

[DOI]

Proceedings of the 43rd Design Automation Conference, 2006

2005

Fault diagnosis and logic debugging using Boolean satisfiability.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Incremental fault diagnosis.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Incremental Design Debugging in a Logic Synthesis Environment.

[BibT_eX]

[DOI]

J. Electron. Test., 2005

Functional Fault Equivalence and Diagnostic Test Generation in Combinational Logic Circuits Using Conventional ATPG.

[BibT_eX]

[DOI]

J. Electron. Test., 2005

Post-Verification Debugging of Hierarchical Designs.

[BibT_eX]

[DOI]

Proceedings of the Sixth International Workshop on Microprocessor Test and Verification (MTV 2005), 2005

Utilizing don't care states in SAT-based bounded sequential problems.

[BibT_eX]

[DOI]

Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

Diagnosing multiple transition faults in the absence of timing information.

[BibT_eX]

[DOI]

Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

Extraction Error Modeling and Automated Model Debugging in High-Performance Low Power Custom Designs.

[BibT_eX]

[DOI]

Paul J. Thadikaran

Srikanth Venkataraman

Proceedings of the 2005 Design, 2005

2004

Logic Rewiring for Delay and Power Minimization.

[BibT_eX]

[DOI]

J. Inf. Sci. Eng., 2004

Debugging Sequential Circuits Using Boolean Satisfiability.

[BibT_eX]

[DOI]

Proceedings of the Fifth International Workshop on Microprocessor Test and Verification (MTV 2004), 2004

Fault equivalence and diagnostic test generation using ATPG.

[BibT_eX]

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Managing Don't Cares in Boolean Satisfiability.

[BibT_eX]

[DOI]

Proceedings of the 2004 Design, 2004

Design diagnosis using Boolean satisfiability.

[BibT_eX]

[DOI]

Alexander Smith

Anastasios Viglas

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003

Extraction Error Analysis, Diagnosis and Correction in Custom-Made High-Performance Designs.

[BibT_eX]

[DOI]

Proceedings of the Fourth International Workshop on Microprocessor Test and Verification, 2003

Fault Diagnosis and Logic Debugging Using Boolean Satisfiability.

[BibT_eX]

[DOI]

Proceedings of the Fourth International Workshop on Microprocessor Test and Verification, 2003

Extraction Error Diagnosis and Correction in High-Performance Designs.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Logic verification based on diagnosis techniques.

[BibT_eX]

[DOI]

Alexander Smith

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002

Design rewiring using ATPG.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Efficient and Exact Diagnosis of Multiple Stuck-At Faults.

[BibT_eX]

Proceedings of the 3rd Latin American Test Workshop, 2002

Design Rewiring Using ATPG.

[BibT_eX]

[DOI]

Mandana Amiri

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Incremental Diagnosis of Multiple Open-Interconnects.

[BibT_eX]

[DOI]

Hiroshi Takahashi

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Design rewiring for power minimization [logic design].

[BibT_eX]

[DOI]

Mandana Amiri

Ivor Ting

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Incremental Diagnosis and Correction of Multiple Faults and Errors.

[BibT_eX]

[DOI]

Proceedings of the 2002 Design, 2002

2001

ATPG Driven Logic Synthesis for Delay and Power Minimization.

[BibT_eX]

Ivor Ting

Proceedings of the 2nd Latin American Test Workshop, 2001

Design rewiring based on diagnosis techniques.

[BibT_eX]

[DOI]

Ivor Ting

Proceedings of ASP-DAC 2001, 2001

2000

Design Optimization Based on Diagnosis Techniques.

[BibT_eX]

Ibrahim N. Haji

Proceedings of the 1st Latin American Test Workshop, 2000

1999

Design error diagnosis and correction via test vector simulation.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

Multiple Design Error Diagnosis and Correction in Digital VLSI Circuits.

[BibT_eX]

[DOI]

Srikanth Venkataraman

W. Kent Fuchs

Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

Correcting multiple design errors in digital VLSI circuits.

[BibT_eX]

[DOI]

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

A hybrid approach to design error detection and correction [VLSI digital circuits].

[BibT_eX]

[DOI]

Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

1998

Multiple Design Error Diagnosis and Correction in Digital VLSI Circuits

[BibT_eX]

[DOI]

PhD thesis, 1998

1997

A Fast Algorithm for Locating and Correcting Simple Design Errors in VLSI Digital Circuits.

[BibT_eX]

[DOI]

Proceedings of the 7th Great Lakes Symposium on VLSI (GLS-VLSI '97), 1997

1995

Efficient Algorithms for Checking the Atomicity of a Run of Read and Write Operations.

[BibT_eX]

[DOI]

Lefteris M. Kirousis